xref: /linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml (revision 34dc1baba215b826e454b8d19e4f24adbeb7d00d) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. CPUFREQ
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11
12description: |
13
14  CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
15  SoCs to manage frequency in hardware. It is capable of controlling frequency
16  for multiple clusters.
17
18properties:
19  compatible:
20    oneOf:
21      - description: v1 of CPUFREQ HW
22        items:
23          - enum:
24              - qcom,qcm2290-cpufreq-hw
25              - qcom,sc7180-cpufreq-hw
26              - qcom,sdm845-cpufreq-hw
27              - qcom,sm6115-cpufreq-hw
28              - qcom,sm6350-cpufreq-hw
29              - qcom,sm8150-cpufreq-hw
30          - const: qcom,cpufreq-hw
31
32      - description: v2 of CPUFREQ HW (EPSS)
33        items:
34          - enum:
35              - qcom,qdu1000-cpufreq-epss
36              - qcom,sa8775p-cpufreq-epss
37              - qcom,sc7280-cpufreq-epss
38              - qcom,sc8280xp-cpufreq-epss
39              - qcom,sm6375-cpufreq-epss
40              - qcom,sm8250-cpufreq-epss
41              - qcom,sm8350-cpufreq-epss
42              - qcom,sm8450-cpufreq-epss
43              - qcom,sm8550-cpufreq-epss
44          - const: qcom,cpufreq-epss
45
46  reg:
47    minItems: 1
48    items:
49      - description: Frequency domain 0 register region
50      - description: Frequency domain 1 register region
51      - description: Frequency domain 2 register region
52      - description: Frequency domain 3 register region
53
54  reg-names:
55    minItems: 1
56    items:
57      - const: freq-domain0
58      - const: freq-domain1
59      - const: freq-domain2
60      - const: freq-domain3
61
62  clocks:
63    items:
64      - description: XO Clock
65      - description: GPLL0 Clock
66
67  clock-names:
68    items:
69      - const: xo
70      - const: alternate
71
72  interrupts:
73    minItems: 1
74    maxItems: 4
75
76  interrupt-names:
77    minItems: 1
78    items:
79      - const: dcvsh-irq-0
80      - const: dcvsh-irq-1
81      - const: dcvsh-irq-2
82      - const: dcvsh-irq-3
83
84  '#freq-domain-cells':
85    const: 1
86
87  '#clock-cells':
88    const: 1
89
90required:
91  - compatible
92  - reg
93  - clocks
94  - clock-names
95  - '#freq-domain-cells'
96
97additionalProperties: false
98
99allOf:
100  - if:
101      properties:
102        compatible:
103          contains:
104            enum:
105              - qcom,qcm2290-cpufreq-hw
106    then:
107      properties:
108        reg:
109          minItems: 1
110          maxItems: 1
111
112        reg-names:
113          minItems: 1
114          maxItems: 1
115
116        interrupts:
117          minItems: 1
118          maxItems: 1
119
120        interrupt-names:
121          minItems: 1
122
123  - if:
124      properties:
125        compatible:
126          contains:
127            enum:
128              - qcom,qdu1000-cpufreq-epss
129              - qcom,sc7180-cpufreq-hw
130              - qcom,sc8280xp-cpufreq-epss
131              - qcom,sdm845-cpufreq-hw
132              - qcom,sm6115-cpufreq-hw
133              - qcom,sm6350-cpufreq-hw
134              - qcom,sm6375-cpufreq-epss
135    then:
136      properties:
137        reg:
138          minItems: 2
139          maxItems: 2
140
141        reg-names:
142          minItems: 2
143          maxItems: 2
144
145        interrupts:
146          minItems: 2
147          maxItems: 2
148
149        interrupt-names:
150          minItems: 2
151
152  - if:
153      properties:
154        compatible:
155          contains:
156            enum:
157              - qcom,sc7280-cpufreq-epss
158              - qcom,sm8250-cpufreq-epss
159              - qcom,sm8350-cpufreq-epss
160              - qcom,sm8450-cpufreq-epss
161              - qcom,sm8550-cpufreq-epss
162    then:
163      properties:
164        reg:
165          minItems: 3
166          maxItems: 3
167
168        reg-names:
169          minItems: 3
170          maxItems: 3
171
172        interrupts:
173          minItems: 3
174          maxItems: 3
175
176        interrupt-names:
177          minItems: 3
178
179  - if:
180      properties:
181        compatible:
182          contains:
183            enum:
184              - qcom,sm8150-cpufreq-hw
185    then:
186      properties:
187        reg:
188          minItems: 3
189          maxItems: 3
190
191        reg-names:
192          minItems: 3
193          maxItems: 3
194
195        # On some SoCs the Prime core shares the LMH irq with Big cores
196        interrupts:
197          minItems: 2
198          maxItems: 2
199
200        interrupt-names:
201          minItems: 2
202
203
204examples:
205  - |
206    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
207    #include <dt-bindings/clock/qcom,rpmh.h>
208
209    // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
210    // switch DCVS state together.
211    cpus {
212      #address-cells = <2>;
213      #size-cells = <0>;
214
215      CPU0: cpu@0 {
216        device_type = "cpu";
217        compatible = "qcom,kryo385";
218        reg = <0x0 0x0>;
219        enable-method = "psci";
220        next-level-cache = <&L2_0>;
221        qcom,freq-domain = <&cpufreq_hw 0>;
222        clocks = <&cpufreq_hw 0>;
223        L2_0: l2-cache {
224          compatible = "cache";
225          cache-unified;
226          cache-level = <2>;
227          next-level-cache = <&L3_0>;
228          L3_0: l3-cache {
229            compatible = "cache";
230            cache-unified;
231            cache-level = <3>;
232          };
233        };
234      };
235
236      CPU1: cpu@100 {
237        device_type = "cpu";
238        compatible = "qcom,kryo385";
239        reg = <0x0 0x100>;
240        enable-method = "psci";
241        next-level-cache = <&L2_100>;
242        qcom,freq-domain = <&cpufreq_hw 0>;
243        clocks = <&cpufreq_hw 0>;
244        L2_100: l2-cache {
245          compatible = "cache";
246          cache-unified;
247          cache-level = <2>;
248          next-level-cache = <&L3_0>;
249        };
250      };
251
252      CPU2: cpu@200 {
253        device_type = "cpu";
254        compatible = "qcom,kryo385";
255        reg = <0x0 0x200>;
256        enable-method = "psci";
257        next-level-cache = <&L2_200>;
258        qcom,freq-domain = <&cpufreq_hw 0>;
259        clocks = <&cpufreq_hw 0>;
260        L2_200: l2-cache {
261          compatible = "cache";
262          cache-unified;
263          cache-level = <2>;
264          next-level-cache = <&L3_0>;
265        };
266      };
267
268      CPU3: cpu@300 {
269        device_type = "cpu";
270        compatible = "qcom,kryo385";
271        reg = <0x0 0x300>;
272        enable-method = "psci";
273        next-level-cache = <&L2_300>;
274        qcom,freq-domain = <&cpufreq_hw 0>;
275        clocks = <&cpufreq_hw 0>;
276        L2_300: l2-cache {
277          compatible = "cache";
278          cache-unified;
279          cache-level = <2>;
280          next-level-cache = <&L3_0>;
281        };
282      };
283
284      CPU4: cpu@400 {
285        device_type = "cpu";
286        compatible = "qcom,kryo385";
287        reg = <0x0 0x400>;
288        enable-method = "psci";
289        next-level-cache = <&L2_400>;
290        qcom,freq-domain = <&cpufreq_hw 1>;
291        clocks = <&cpufreq_hw 1>;
292        L2_400: l2-cache {
293          compatible = "cache";
294          cache-unified;
295          cache-level = <2>;
296          next-level-cache = <&L3_0>;
297        };
298      };
299
300      CPU5: cpu@500 {
301        device_type = "cpu";
302        compatible = "qcom,kryo385";
303        reg = <0x0 0x500>;
304        enable-method = "psci";
305        next-level-cache = <&L2_500>;
306        qcom,freq-domain = <&cpufreq_hw 1>;
307        clocks = <&cpufreq_hw 1>;
308        L2_500: l2-cache {
309          compatible = "cache";
310          cache-unified;
311          cache-level = <2>;
312          next-level-cache = <&L3_0>;
313        };
314      };
315
316      CPU6: cpu@600 {
317        device_type = "cpu";
318        compatible = "qcom,kryo385";
319        reg = <0x0 0x600>;
320        enable-method = "psci";
321        next-level-cache = <&L2_600>;
322        qcom,freq-domain = <&cpufreq_hw 1>;
323        clocks = <&cpufreq_hw 1>;
324        L2_600: l2-cache {
325          compatible = "cache";
326          cache-unified;
327          cache-level = <2>;
328          next-level-cache = <&L3_0>;
329        };
330      };
331
332      CPU7: cpu@700 {
333        device_type = "cpu";
334        compatible = "qcom,kryo385";
335        reg = <0x0 0x700>;
336        enable-method = "psci";
337        next-level-cache = <&L2_700>;
338        qcom,freq-domain = <&cpufreq_hw 1>;
339        clocks = <&cpufreq_hw 1>;
340        L2_700: l2-cache {
341          compatible = "cache";
342          cache-unified;
343          cache-level = <2>;
344          next-level-cache = <&L3_0>;
345        };
346      };
347    };
348
349    soc {
350      #address-cells = <1>;
351      #size-cells = <1>;
352
353      cpufreq@17d43000 {
354        compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
355        reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
356        reg-names = "freq-domain0", "freq-domain1";
357
358        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
359        clock-names = "xo", "alternate";
360
361        #freq-domain-cells = <1>;
362        #clock-cells = <1>;
363      };
364    };
365...
366