xref: /linux/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek's CPUFREQ
8
9maintainers:
10  - Hector Yuan <hector.yuan@mediatek.com>
11
12description:
13  CPUFREQ HW is a hardware engine used by MediaTek SoCs to
14  manage frequency in hardware. It is capable of controlling
15  frequency for multiple clusters.
16
17properties:
18  compatible:
19    const: mediatek,cpufreq-hw
20
21  reg:
22    minItems: 1
23    maxItems: 2
24    description:
25      Addresses and sizes for the memory of the HW bases in
26      each frequency domain. Each entry corresponds to
27      a register bank for each frequency domain present.
28
29  "#performance-domain-cells":
30    description:
31      Number of cells in a performance domain specifier.
32      Set const to 1 here for nodes providing multiple
33      performance domains.
34    const: 1
35
36required:
37  - compatible
38  - reg
39  - "#performance-domain-cells"
40
41additionalProperties: false
42
43examples:
44  - |
45    cpus {
46            #address-cells = <1>;
47            #size-cells = <0>;
48
49            cpu0: cpu@0 {
50                device_type = "cpu";
51                compatible = "arm,cortex-a55";
52                enable-method = "psci";
53                performance-domains = <&performance 0>;
54                reg = <0x000>;
55            };
56    };
57
58    /* ... */
59
60    soc {
61        #address-cells = <2>;
62        #size-cells = <2>;
63
64        performance: performance-controller@11bc00 {
65            compatible = "mediatek,cpufreq-hw";
66            reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
67
68            #performance-domain-cells = <1>;
69        };
70    };
71