1Generic cpufreq driver 2 3It is a generic DT based cpufreq driver for frequency management. It supports 4both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share 5clock and voltage across all CPUs. 6 7Both required and optional properties listed below must be defined 8under node /cpus/cpu@0. 9 10Required properties: 11- None 12 13Optional properties: 14- operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for 15 details. OPPs *must* be supplied either via DT, i.e. this property, or 16 populated at runtime. 17- clock-latency: Specify the possible maximum transition latency for clock, 18 in unit of nanoseconds. 19- voltage-tolerance: Specify the CPU voltage tolerance in percentage. 20- #cooling-cells: 21 Please refer to 22 Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml. 23 24Examples: 25 26cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 compatible = "arm,cortex-a9"; 32 reg = <0>; 33 next-level-cache = <&L2>; 34 operating-points = < 35 /* kHz uV */ 36 792000 1100000 37 396000 950000 38 198000 850000 39 >; 40 clock-latency = <61036>; /* two CLK32 periods */ 41 #cooling-cells = <2>; 42 }; 43 44 cpu@1 { 45 compatible = "arm,cortex-a9"; 46 reg = <1>; 47 next-level-cache = <&L2>; 48 }; 49 50 cpu@2 { 51 compatible = "arm,cortex-a9"; 52 reg = <2>; 53 next-level-cache = <&L2>; 54 }; 55 56 cpu@3 { 57 compatible = "arm,cortex-a9"; 58 reg = <3>; 59 next-level-cache = <&L2>; 60 }; 61}; 62