xref: /linux/Documentation/devicetree/bindings/cpufreq/brcm,stb-avs-cpu-freq.txt (revision e5c86679d5e864947a52fb31e45a425dea3e7fa9) 
1Broadcom AVS mail box and interrupt register bindings
2=====================================================
3
4A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
5references the mailbox register used to communicate with the AVS CPU[1]. The
6second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
7the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
8command sent to it by a driver. Interrupting the AVS CPU is mandatory for
9commands to be processed.
10
11The interface also requires a reference to the AVS host interrupt controller,
12so a driver can react to interrupts generated by the AVS CPU whenever a command
13has been processed. See [2] for more information on the brcm,l2-intc node.
14
15[1] The AVS CPU is an independent co-processor that runs proprietary
16firmware. On some SoCs, this firmware supports DFS and DVFS in addition to
17Adaptive Voltage Scaling.
18
19[2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
20
21
22Node brcm,avs-cpu-data-mem
23--------------------------
24
25Required properties:
26- compatible: must include: brcm,avs-cpu-data-mem and
27              should include: one of brcm,bcm7271-avs-cpu-data-mem or
28                              brcm,bcm7268-avs-cpu-data-mem
29- reg: Specifies base physical address and size of the registers.
30- interrupts: The interrupt that the AVS CPU will use to interrupt the host
31              when a command completed.
32- interrupt-parent: The interrupt controller the above interrupt is routed
33                    through.
34- interrupt-names: The name of the interrupt used to interrupt the host.
35
36Optional properties:
37- None
38
39Node brcm,avs-cpu-l2-intr
40-------------------------
41
42Required properties:
43- compatible: must include: brcm,avs-cpu-l2-intr and
44              should include: one of brcm,bcm7271-avs-cpu-l2-intr or
45                              brcm,bcm7268-avs-cpu-l2-intr
46- reg: Specifies base physical address and size of the registers.
47
48Optional properties:
49- None
50
51
52Example
53=======
54
55	avs_host_l2_intc: interrupt-controller@f04d1200 {
56		#interrupt-cells = <1>;
57		compatible = "brcm,l2-intc";
58		interrupt-parent = <&intc>;
59		reg = <0xf04d1200 0x48>;
60		interrupt-controller;
61		interrupts = <0x0 0x19 0x0>;
62		interrupt-names = "avs";
63	};
64
65	avs-cpu-data-mem@f04c4000 {
66		compatible = "brcm,bcm7271-avs-cpu-data-mem",
67				"brcm,avs-cpu-data-mem";
68		reg = <0xf04c4000 0x60>;
69		interrupts = <0x1a>;
70		interrupt-parent = <&avs_host_l2_intc>;
71		interrupt-names = "sw_intr";
72	};
73
74	avs-cpu-l2-intr@f04d1100 {
75		compatible = "brcm,bcm7271-avs-cpu-l2-intr",
76				"brcm,avs-cpu-l2-intr";
77		reg = <0xf04d1100 0x10>;
78	};
79