xref: /linux/Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml (revision 9f2c9170934eace462499ba0bfe042cc72900173) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Apple SoC cluster cpufreq device
8
9maintainers:
10  - Hector Martin <marcan@marcan.st>
11
12description: |
13  Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
14  the cluster management register block. This binding uses the standard
15  operating-points-v2 table to define the CPU performance states, with the
16  opp-level property specifying the hardware p-state index for that level.
17
18properties:
19  compatible:
20    oneOf:
21      - items:
22          - enum:
23              - apple,t8103-cluster-cpufreq
24              - apple,t8112-cluster-cpufreq
25          - const: apple,cluster-cpufreq
26      - items:
27          - const: apple,t6000-cluster-cpufreq
28          - const: apple,t8103-cluster-cpufreq
29          - const: apple,cluster-cpufreq
30
31  reg:
32    maxItems: 1
33
34  '#performance-domain-cells':
35    const: 0
36
37required:
38  - compatible
39  - reg
40  - '#performance-domain-cells'
41
42additionalProperties: false
43
44examples:
45  - |
46    // This example shows a single CPU per domain and 2 domains,
47    // with two p-states per domain.
48    // Shipping hardware has 2-4 CPUs per domain and 2-6 domains.
49    cpus {
50      #address-cells = <2>;
51      #size-cells = <0>;
52
53      cpu@0 {
54        compatible = "apple,icestorm";
55        device_type = "cpu";
56        reg = <0x0 0x0>;
57        operating-points-v2 = <&ecluster_opp>;
58        performance-domains = <&cpufreq_e>;
59      };
60
61      cpu@10100 {
62        compatible = "apple,firestorm";
63        device_type = "cpu";
64        reg = <0x0 0x10100>;
65        operating-points-v2 = <&pcluster_opp>;
66        performance-domains = <&cpufreq_p>;
67      };
68    };
69
70    ecluster_opp: opp-table-0 {
71      compatible = "operating-points-v2";
72      opp-shared;
73
74      opp01 {
75        opp-hz = /bits/ 64 <600000000>;
76        opp-level = <1>;
77        clock-latency-ns = <7500>;
78      };
79      opp02 {
80        opp-hz = /bits/ 64 <972000000>;
81        opp-level = <2>;
82        clock-latency-ns = <22000>;
83      };
84    };
85
86    pcluster_opp: opp-table-1 {
87      compatible = "operating-points-v2";
88      opp-shared;
89
90      opp01 {
91        opp-hz = /bits/ 64 <600000000>;
92        opp-level = <1>;
93        clock-latency-ns = <8000>;
94      };
95      opp02 {
96        opp-hz = /bits/ 64 <828000000>;
97        opp-level = <2>;
98        clock-latency-ns = <19000>;
99      };
100    };
101
102    soc {
103      #address-cells = <2>;
104      #size-cells = <2>;
105
106      cpufreq_e: performance-controller@210e20000 {
107        compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
108        reg = <0x2 0x10e20000 0 0x1000>;
109        #performance-domain-cells = <0>;
110      };
111
112      cpufreq_p: performance-controller@211e20000 {
113        compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
114        reg = <0x2 0x11e20000 0 0x1000>;
115        #performance-domain-cells = <0>;
116      };
117    };
118