xref: /linux/Documentation/devicetree/bindings/cpufreq/airoha,en7581-cpufreq.yaml (revision f4b9d3bf44d59ca4489bd8c489539c27c02e5c6a)
1*ab16dfb9SChristian Marangi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*ab16dfb9SChristian Marangi%YAML 1.2
3*ab16dfb9SChristian Marangi---
4*ab16dfb9SChristian Marangi$id: http://devicetree.org/schemas/cpufreq/airoha,en7581-cpufreq.yaml#
5*ab16dfb9SChristian Marangi$schema: http://devicetree.org/meta-schemas/core.yaml#
6*ab16dfb9SChristian Marangi
7*ab16dfb9SChristian Marangititle: Airoha EN7581 CPUFreq
8*ab16dfb9SChristian Marangi
9*ab16dfb9SChristian Marangimaintainers:
10*ab16dfb9SChristian Marangi  - Christian Marangi <ansuelsmth@gmail.com>
11*ab16dfb9SChristian Marangi
12*ab16dfb9SChristian Marangidescription: |
13*ab16dfb9SChristian Marangi  On newer Airoha SoC, CPU Frequency is scaled indirectly with SMC commands
14*ab16dfb9SChristian Marangi  to ATF.
15*ab16dfb9SChristian Marangi
16*ab16dfb9SChristian Marangi  A virtual clock is exposed. This virtual clock is a get-only clock and
17*ab16dfb9SChristian Marangi  is used to expose the current global CPU clock. The frequency info comes
18*ab16dfb9SChristian Marangi  by the output of the SMC command that reports the clock in MHz.
19*ab16dfb9SChristian Marangi
20*ab16dfb9SChristian Marangi  The SMC sets the CPU clock by providing an index, this is modelled as
21*ab16dfb9SChristian Marangi  performance states in a power domain.
22*ab16dfb9SChristian Marangi
23*ab16dfb9SChristian Marangi  CPUs can't be individually scaled as the CPU frequency is shared across
24*ab16dfb9SChristian Marangi  all CPUs and is global.
25*ab16dfb9SChristian Marangi
26*ab16dfb9SChristian Marangiproperties:
27*ab16dfb9SChristian Marangi  compatible:
28*ab16dfb9SChristian Marangi    const: airoha,en7581-cpufreq
29*ab16dfb9SChristian Marangi
30*ab16dfb9SChristian Marangi  '#clock-cells':
31*ab16dfb9SChristian Marangi    const: 0
32*ab16dfb9SChristian Marangi
33*ab16dfb9SChristian Marangi  '#power-domain-cells':
34*ab16dfb9SChristian Marangi    const: 0
35*ab16dfb9SChristian Marangi
36*ab16dfb9SChristian Marangi  operating-points-v2: true
37*ab16dfb9SChristian Marangi
38*ab16dfb9SChristian Marangirequired:
39*ab16dfb9SChristian Marangi  - compatible
40*ab16dfb9SChristian Marangi  - '#clock-cells'
41*ab16dfb9SChristian Marangi  - '#power-domain-cells'
42*ab16dfb9SChristian Marangi  - operating-points-v2
43*ab16dfb9SChristian Marangi
44*ab16dfb9SChristian MarangiadditionalProperties: false
45*ab16dfb9SChristian Marangi
46*ab16dfb9SChristian Marangiexamples:
47*ab16dfb9SChristian Marangi  - |
48*ab16dfb9SChristian Marangi    performance-domain {
49*ab16dfb9SChristian Marangi        compatible = "airoha,en7581-cpufreq";
50*ab16dfb9SChristian Marangi
51*ab16dfb9SChristian Marangi        operating-points-v2 = <&cpu_smcc_opp_table>;
52*ab16dfb9SChristian Marangi
53*ab16dfb9SChristian Marangi        #power-domain-cells = <0>;
54*ab16dfb9SChristian Marangi        #clock-cells = <0>;
55*ab16dfb9SChristian Marangi    };
56