1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Xilinx clocking wizard 8 9maintainers: 10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> 11 12description: 13 The clocking wizard is a soft ip clocking block of Xilinx versal. It 14 reads required input clock frequencies from the devicetree and acts as clock 15 clock output. 16 17properties: 18 compatible: 19 enum: 20 - xlnx,clocking-wizard 21 - xlnx,clocking-wizard-v5.2 22 - xlnx,clocking-wizard-v6.0 23 - xlnx,versal-clk-wizard 24 25 reg: 26 maxItems: 1 27 28 "#clock-cells": 29 const: 1 30 31 clocks: 32 items: 33 - description: clock input 34 - description: axi clock 35 36 clock-names: 37 items: 38 - const: clk_in1 39 - const: s_axi_aclk 40 41 xlnx,static-config: 42 $ref: /schemas/types.yaml#/definitions/flag 43 description: 44 Indicate whether the core has been configured without support for dynamic 45 runtime reconfguration of the clocking primitive MMCM/PLL. 46 47 xlnx,speed-grade: 48 $ref: /schemas/types.yaml#/definitions/uint32 49 enum: [1, 2, 3] 50 description: 51 Speed grade of the device. Higher the speed grade faster is the FPGA device. 52 53 xlnx,nr-outputs: 54 $ref: /schemas/types.yaml#/definitions/uint32 55 minimum: 1 56 maximum: 8 57 description: 58 Number of outputs. 59 60required: 61 - compatible 62 - reg 63 - "#clock-cells" 64 - clocks 65 - clock-names 66 - xlnx,speed-grade 67 - xlnx,nr-outputs 68 69additionalProperties: false 70 71examples: 72 - | 73 clock-controller@b0000000 { 74 compatible = "xlnx,clocking-wizard"; 75 reg = <0xb0000000 0x10000>; 76 #clock-cells = <1>; 77 xlnx,static-config; 78 xlnx,speed-grade = <1>; 79 xlnx,nr-outputs = <6>; 80 clock-names = "clk_in1", "s_axi_aclk"; 81 clocks = <&clkc 15>, <&clkc 15>; 82 }; 83... 84