xref: /linux/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml (revision 352546805a44871b68affea09a2fbd5a48e452d0)

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/clock/xlnx,versal-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx Versal clock controller

maintainers:
  - Michal Simek <michal.simek@xilinx.com>
  - Jolly Shah <jolly.shah@xilinx.com>
  - Rajan Vaja <rajan.vaja@xilinx.com>

description: |
  The clock controller is a hardware block of Xilinx versal clock tree. It
  reads required input clock frequencies from the devicetree and acts as clock
  provider for all clock consumers of PS clocks.

select: false

properties:
  compatible:
    const: xlnx,versal-clk

  "#clock-cells":
    const: 1

  clocks:
    description: List of clock specifiers which are external input
      clocks to the given clock controller.
    items:
      - description: reference clock
      - description: alternate reference clock
      - description: alternate reference clock for programmable logic

  clock-names:
    items:
      - const: ref
      - const: alt_ref
      - const: pl_alt_ref

required:
  - compatible
  - "#clock-cells"
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    firmware {
      zynqmp_firmware: zynqmp-firmware {
        compatible = "xlnx,zynqmp-firmware";
        method = "smc";
        versal_clk: clock-controller {
          #clock-cells = <1>;
          compatible = "xlnx,versal-clk";
          clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
          clock-names = "ref", "alt_ref", "pl_alt_ref";
        };
      };
    };
...