xref: /linux/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml (revision 42ac0be18bfa09c03f52244f7c3e15c89b38532f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx clocking wizard
8
9maintainers:
10  - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11
12description:
13  The clocking wizard is a soft ip clocking block of Xilinx versal. It
14  reads required input clock frequencies from the devicetree and acts as clock
15  clock output.
16
17properties:
18  compatible:
19    enum:
20      - xlnx,clocking-wizard
21      - xlnx,clocking-wizard-v5.2
22      - xlnx,clocking-wizard-v6.0
23      - xlnx,versal-clk-wizard
24
25
26  reg:
27    maxItems: 1
28
29  "#clock-cells":
30    const: 1
31
32  clocks:
33    items:
34      - description: clock input
35      - description: axi clock
36
37  clock-names:
38    items:
39      - const: clk_in1
40      - const: s_axi_aclk
41
42
43  xlnx,speed-grade:
44    $ref: /schemas/types.yaml#/definitions/uint32
45    enum: [1, 2, 3]
46    description:
47      Speed grade of the device. Higher the speed grade faster is the FPGA device.
48
49  xlnx,nr-outputs:
50    $ref: /schemas/types.yaml#/definitions/uint32
51    minimum: 1
52    maximum: 8
53    description:
54      Number of outputs.
55
56required:
57  - compatible
58  - reg
59  - "#clock-cells"
60  - clocks
61  - clock-names
62  - xlnx,speed-grade
63  - xlnx,nr-outputs
64
65additionalProperties: false
66
67examples:
68  - |
69    clock-controller@b0000000  {
70        compatible = "xlnx,clocking-wizard";
71        reg = <0xb0000000 0x10000>;
72        #clock-cells = <1>;
73        xlnx,speed-grade = <1>;
74        xlnx,nr-outputs = <6>;
75        clock-names = "clk_in1", "s_axi_aclk";
76        clocks = <&clkc 15>, <&clkc 15>;
77    };
78...
79