11f2c5fd5SJingchang Lu* Clock bindings for Freescale Vybrid VF610 SOC 21f2c5fd5SJingchang Lu 31f2c5fd5SJingchang LuRequired properties: 41f2c5fd5SJingchang Lu- compatible: Should be "fsl,vf610-ccm" 51f2c5fd5SJingchang Lu- reg: Address and length of the register set 61f2c5fd5SJingchang Lu- #clock-cells: Should be <1> 71f2c5fd5SJingchang Lu 83f3ebfb8SStefan AgnerOptional properties: 93f3ebfb8SStefan Agner- clocks: list of clock identifiers which are external input clocks to the 103f3ebfb8SStefan Agner given clock controller. Please refer the next section to find 113f3ebfb8SStefan Agner the input clocks for a given controller. 12*47aab533SBjorn Helgaas- clock-names: list of names of clocks which are external input clocks to the 133f3ebfb8SStefan Agner given clock controller. 143f3ebfb8SStefan Agner 153f3ebfb8SStefan AgnerInput clocks for top clock controller: 163f3ebfb8SStefan Agner - sxosc (external crystal oscillator 32KHz, recommended) 173f3ebfb8SStefan Agner - fxosc (external crystal oscillator 24MHz, recommended) 183f3ebfb8SStefan Agner - audio_ext 193f3ebfb8SStefan Agner - enet_ext 203f3ebfb8SStefan Agner 211f2c5fd5SJingchang LuThe clock consumer should specify the desired clock by having the clock 221f2c5fd5SJingchang LuID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h 231f2c5fd5SJingchang Lufor the full list of VF610 clock IDs. 241f2c5fd5SJingchang Lu 251f2c5fd5SJingchang LuExamples: 261f2c5fd5SJingchang Lu 271f2c5fd5SJingchang Luclks: ccm@4006b000 { 281f2c5fd5SJingchang Lu compatible = "fsl,vf610-ccm"; 291f2c5fd5SJingchang Lu reg = <0x4006b000 0x1000>; 301f2c5fd5SJingchang Lu #clock-cells = <1>; 313f3ebfb8SStefan Agner clocks = <&sxosc>, <&fxosc>; 323f3ebfb8SStefan Agner clock-names = "sxosc", "fxosc"; 331f2c5fd5SJingchang Lu}; 341f2c5fd5SJingchang Lu 351f2c5fd5SJingchang Luuart1: serial@40028000 { 361f2c5fd5SJingchang Lu compatible = "fsl,vf610-uart"; 371f2c5fd5SJingchang Lu reg = <0x40028000 0x1000>; 381f2c5fd5SJingchang Lu interrupts = <0 62 0x04>; 391f2c5fd5SJingchang Lu clocks = <&clks VF610_CLK_UART1>; 401f2c5fd5SJingchang Lu clock-names = "ipg"; 411f2c5fd5SJingchang Lu}; 42