1Binding for Texas Instruments gate clock. 2 3Binding status: Unstable - ABI compatibility may be broken in the future 4 5This binding uses the common clock binding[1]. This clock is 6quite much similar to the basic gate-clock [2], however, 7it supports a number of additional features. If no register 8is provided for this clock, the code assumes that a clockdomain 9will be controlled instead and the corresponding hw-ops for 10that is used. 11 12[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 13[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml 14[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt 15 16Required properties: 17- compatible : shall be one of: 18 "ti,gate-clock" - basic gate clock 19 "ti,wait-gate-clock" - gate clock which waits until clock is active before 20 returning from clk_enable() 21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling 22 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling 23 "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional 24 clock directly from a clockdomain, see [3] how 25 to map clockdomains properly 26 "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling, 27 required for a hardware errata 28 "ti,composite-gate-clock" - composite gate clock, to be part of composite 29 clock 30 "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait 31 for clock to be active before returning 32 from clk_enable() 33- #clock-cells : from common clock binding; shall be set to 0 34- clocks : link to phandle of parent clock 35- reg : offset for register controlling adjustable gate, not needed for 36 ti,clkdm-gate-clock type 37 38Optional properties: 39- clock-output-names : from common clock binding. 40- ti,bit-shift : bit shift for programming the clock gate, invalid for 41 ti,clkdm-gate-clock type 42- ti,set-bit-to-disable : inverts default gate programming. Setting the bit 43 gates the clock and clearing the bit ungates the clock. 44 45Examples: 46 mmchs2_fck: mmchs2_fck@48004a00 { 47 #clock-cells = <0>; 48 compatible = "ti,gate-clock"; 49 clocks = <&core_96m_fck>; 50 reg = <0x0a00>; 51 ti,bit-shift = <25>; 52 }; 53 54 uart4_fck_am35xx: uart4_fck_am35xx { 55 #clock-cells = <0>; 56 compatible = "ti,wait-gate-clock"; 57 clocks = <&core_48m_fck>; 58 reg = <0x0a00>; 59 ti,bit-shift = <23>; 60 }; 61 62 dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 { 63 #clock-cells = <0>; 64 compatible = "ti,dss-gate-clock"; 65 clocks = <&dpll4_m4x2_ck>; 66 reg = <0x0e00>; 67 ti,bit-shift = <0>; 68 }; 69 70 emac_ick: emac_ick@4800259c { 71 #clock-cells = <0>; 72 compatible = "ti,am35xx-gate-clock"; 73 clocks = <&ipss_ick>; 74 reg = <0x059c>; 75 ti,bit-shift = <1>; 76 }; 77 78 emu_src_ck: emu_src_ck { 79 #clock-cells = <0>; 80 compatible = "ti,clkdm-gate-clock"; 81 clocks = <&emu_src_mux_ck>; 82 }; 83 84 dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 { 85 #clock-cells = <0>; 86 compatible = "ti,hsdiv-gate-clock"; 87 clocks = <&dpll4_m2x2_mul_ck>; 88 ti,bit-shift = <0x1b>; 89 reg = <0x0d00>; 90 ti,set-bit-to-disable; 91 }; 92 93 vlynq_gate_fck: vlynq_gate_fck { 94 #clock-cells = <0>; 95 compatible = "ti,composite-gate-clock"; 96 clocks = <&core_ck>; 97 ti,bit-shift = <3>; 98 reg = <0x0200>; 99 }; 100 101 sys_clkout2_src_gate: sys_clkout2_src_gate { 102 #clock-cells = <0>; 103 compatible = "ti,composite-no-wait-gate-clock"; 104 clocks = <&core_ck>; 105 ti,bit-shift = <15>; 106 reg = <0x0070>; 107 }; 108