1Binding for Texas Instruments gate clock. 2 3This binding uses the common clock binding[1]. This clock is 4quite much similar to the basic gate-clock [2], however, 5it supports a number of additional features. If no register 6is provided for this clock, the code assumes that a clockdomain 7will be controlled instead and the corresponding hw-ops for 8that is used. 9 10[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 11[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml 12[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt 13 14Required properties: 15- compatible : shall be one of: 16 "ti,gate-clock" - basic gate clock 17 "ti,wait-gate-clock" - gate clock which waits until clock is active before 18 returning from clk_enable() 19 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling 20 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling 21 "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional 22 clock directly from a clockdomain, see [3] how 23 to map clockdomains properly 24 "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling, 25 required for a hardware errata 26 "ti,composite-gate-clock" - composite gate clock, to be part of composite 27 clock 28 "ti,composite-no-wait-gate-clock" - composite gate clock that does not wait 29 for clock to be active before returning 30 from clk_enable() 31- #clock-cells : from common clock binding; shall be set to 0 32- clocks : link to phandle of parent clock 33- reg : offset for register controlling adjustable gate, not needed for 34 ti,clkdm-gate-clock type 35 36Optional properties: 37- clock-output-names : from common clock binding. 38- ti,bit-shift : bit shift for programming the clock gate, invalid for 39 ti,clkdm-gate-clock type 40- ti,set-bit-to-disable : inverts default gate programming. Setting the bit 41 gates the clock and clearing the bit ungates the clock. 42 43Examples: 44 mmchs2_fck: mmchs2_fck@48004a00 { 45 #clock-cells = <0>; 46 compatible = "ti,gate-clock"; 47 clocks = <&core_96m_fck>; 48 reg = <0x0a00>; 49 ti,bit-shift = <25>; 50 }; 51 52 uart4_fck_am35xx: uart4_fck_am35xx { 53 #clock-cells = <0>; 54 compatible = "ti,wait-gate-clock"; 55 clocks = <&core_48m_fck>; 56 reg = <0x0a00>; 57 ti,bit-shift = <23>; 58 }; 59 60 dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 { 61 #clock-cells = <0>; 62 compatible = "ti,dss-gate-clock"; 63 clocks = <&dpll4_m4x2_ck>; 64 reg = <0x0e00>; 65 ti,bit-shift = <0>; 66 }; 67 68 emac_ick: emac_ick@4800259c { 69 #clock-cells = <0>; 70 compatible = "ti,am35xx-gate-clock"; 71 clocks = <&ipss_ick>; 72 reg = <0x059c>; 73 ti,bit-shift = <1>; 74 }; 75 76 emu_src_ck: emu_src_ck { 77 #clock-cells = <0>; 78 compatible = "ti,clkdm-gate-clock"; 79 clocks = <&emu_src_mux_ck>; 80 }; 81 82 dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 { 83 #clock-cells = <0>; 84 compatible = "ti,hsdiv-gate-clock"; 85 clocks = <&dpll4_m2x2_mul_ck>; 86 ti,bit-shift = <0x1b>; 87 reg = <0x0d00>; 88 ti,set-bit-to-disable; 89 }; 90 91 vlynq_gate_fck: vlynq_gate_fck { 92 #clock-cells = <0>; 93 compatible = "ti,composite-gate-clock"; 94 clocks = <&core_ck>; 95 ti,bit-shift = <3>; 96 reg = <0x0200>; 97 }; 98 99 sys_clkout2_src_gate: sys_clkout2_src_gate { 100 #clock-cells = <0>; 101 compatible = "ti,composite-no-wait-gate-clock"; 102 clocks = <&core_ck>; 103 ti,bit-shift = <15>; 104 reg = <0x0070>; 105 }; 106