1*163152cbSTony LindgrenBinding for Texas Instruments FAPLL clock. 2*163152cbSTony Lindgren 3*163152cbSTony LindgrenBinding status: Unstable - ABI compatibility may be broken in the future 4*163152cbSTony Lindgren 5*163152cbSTony LindgrenThis binding uses the common clock binding[1]. It assumes a 6*163152cbSTony Lindgrenregister-mapped FAPLL with usually two selectable input clocks 7*163152cbSTony Lindgren(reference clock and bypass clock), and one or more child 8*163152cbSTony Lindgrensyntesizers. 9*163152cbSTony Lindgren 10*163152cbSTony Lindgren[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 11*163152cbSTony Lindgren 12*163152cbSTony LindgrenRequired properties: 13*163152cbSTony Lindgren- compatible : shall be "ti,dm816-fapll-clock" 14*163152cbSTony Lindgren- #clock-cells : from common clock binding; shall be set to 0. 15*163152cbSTony Lindgren- clocks : link phandles of parent clocks (clk-ref and clk-bypass) 16*163152cbSTony Lindgren- reg : address and length of the register set for controlling the FAPLL. 17*163152cbSTony Lindgren 18*163152cbSTony LindgrenExamples: 19*163152cbSTony Lindgren main_fapll: main_fapll { 20*163152cbSTony Lindgren #clock-cells = <1>; 21*163152cbSTony Lindgren compatible = "ti,dm816-fapll-clock"; 22*163152cbSTony Lindgren reg = <0x400 0x40>; 23*163152cbSTony Lindgren clocks = <&sys_clkin_ck &sys_clkin_ck>; 24*163152cbSTony Lindgren clock-indices = <1>, <2>, <3>, <4>, <5>, 25*163152cbSTony Lindgren <6>, <7>; 26*163152cbSTony Lindgren clock-output-names = "main_pll_clk1", 27*163152cbSTony Lindgren "main_pll_clk2", 28*163152cbSTony Lindgren "main_pll_clk3", 29*163152cbSTony Lindgren "main_pll_clk4", 30*163152cbSTony Lindgren "main_pll_clk5", 31*163152cbSTony Lindgren "main_pll_clk6", 32*163152cbSTony Lindgren "main_pll_clk7"; 33*163152cbSTony Lindgren }; 34