xref: /linux/Documentation/devicetree/bindings/clock/ti,lmk04832.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Texas Instruments LMK04832 Clock Controller
8
9maintainers:
10  - Liam Beguin <liambeguin@gmail.com>
11
12description: |
13  Devicetree binding for the LMK04832, a clock conditioner with JEDEC JESD204B
14  support. The LMK04832 is pin compatible with the LMK0482x family.
15
16  Link to datasheet, https://www.ti.com/lit/ds/symlink/lmk04832.pdf
17
18properties:
19  compatible:
20    enum:
21      - ti,lmk04832
22
23  reg:
24    maxItems: 1
25
26  '#address-cells':
27    const: 1
28
29  '#size-cells':
30    const: 0
31
32  '#clock-cells':
33    const: 1
34
35  spi-max-frequency:
36    maximum: 5000000
37
38  clocks:
39    items:
40      - description: PLL2 reference clock.
41
42  clock-names:
43    items:
44      - const: oscin
45
46  reset-gpios:
47    maxItems: 1
48
49  ti,spi-4wire-rdbk:
50    description: |
51      Select SPI 4wire readback pin configuration.
52      Available readback pins are,
53        CLKin_SEL0 0
54        CLKin_SEL1 1
55        RESET 2
56    $ref: /schemas/types.yaml#/definitions/uint32
57    enum: [0, 1, 2]
58    default: 1
59
60  ti,vco-hz:
61    description: Optional to set VCO frequency of the PLL in Hertz.
62
63  ti,sysref-ddly:
64    description: SYSREF digital delay value.
65    $ref: /schemas/types.yaml#/definitions/uint32
66    minimum: 8
67    maximum: 8191
68    default: 8
69
70  ti,sysref-mux:
71    description: |
72      SYSREF Mux configuration.
73      Available options are,
74        Normal SYNC 0
75        Re-clocked 1
76        SYSREF Pulser 2
77        SYSREF Continuous 3
78    $ref: /schemas/types.yaml#/definitions/uint32
79    enum: [0, 1, 2, 3]
80    default: 3
81
82  ti,sync-mode:
83    description: SYNC pin configuration.
84    $ref: /schemas/types.yaml#/definitions/uint32
85    enum: [0, 1, 2]
86    default: 1
87
88  ti,sysref-pulse-count:
89    description:
90      Number of SYSREF pulses to send when SYSREF is not in continuous mode.
91    $ref: /schemas/types.yaml#/definitions/uint32
92    enum: [1, 2, 4, 8]
93    default: 4
94
95patternProperties:
96  "@[0-9a-d]+$":
97    type: object
98    description:
99      Child nodes used to configure output clocks.
100
101    properties:
102      reg:
103        description:
104          clock output identifier.
105        minimum: 0
106        maximum: 13
107
108      ti,clkout-fmt:
109        description:
110          Clock output format.
111          Available options are,
112            Powerdown 0x00
113            LVDS 0x01
114            HSDS 6 mA 0x02
115            HSDS 8 mA 0x03
116            LVPECL 1600 mV 0x04
117            LVPECL 2000 mV 0x05
118            LCPECL 0x06
119            CML 16 mA 0x07
120            CML 24 mA 0x08
121            CML 32 mA 0x09
122            CMOS (Off/Inverted) 0x0a
123            CMOS (Normal/Off) 0x0b
124            CMOS (Inverted/Inverted) 0x0c
125            CMOS (Inverted/Normal) 0x0d
126            CMOS (Normal/Inverted) 0x0e
127            CMOS (Normal/Normal) 0x0f
128        $ref: /schemas/types.yaml#/definitions/uint32
129        minimum: 0
130        maximum: 15
131
132      ti,clkout-sysref:
133        description:
134          Select SYSREF clock path for output clock.
135        type: boolean
136
137    required:
138      - reg
139
140    additionalProperties: false
141
142required:
143  - compatible
144  - reg
145  - '#clock-cells'
146  - clocks
147  - clock-names
148
149additionalProperties: false
150
151examples:
152  - |
153    clocks {
154        lmk04832_oscin: oscin {
155            compatible = "fixed-clock";
156
157            #clock-cells = <0>;
158            clock-frequency = <122880000>;
159            clock-output-names = "lmk04832-oscin";
160        };
161    };
162
163    spi {
164        #address-cells = <1>;
165        #size-cells = <0>;
166
167        lmk04832: clock-controller@0 {
168            #address-cells = <1>;
169            #size-cells = <0>;
170
171            reg = <0>;
172
173            compatible = "ti,lmk04832";
174            spi-max-frequency = <781250>;
175
176            reset-gpios = <&gpio_lmk 0 0 0>;
177
178            #clock-cells = <1>;
179            clocks = <&lmk04832_oscin>;
180            clock-names = "oscin";
181
182            ti,spi-4wire-rdbk = <0>;
183            ti,vco-hz = <2457600000>;
184
185            assigned-clocks =
186                <&lmk04832 0>, <&lmk04832 1>,
187                <&lmk04832 2>, <&lmk04832 3>,
188                <&lmk04832 4>,
189                <&lmk04832 6>, <&lmk04832 7>,
190                <&lmk04832 10>, <&lmk04832 11>;
191            assigned-clock-rates =
192                <122880000>, <384000>,
193                <122880000>, <384000>,
194                <122880000>,
195                <153600000>, <384000>,
196                <614400000>, <384000>;
197
198            clkout0@0 {
199                reg = <0>;
200                ti,clkout-fmt = <0x01>; // LVDS
201            };
202
203            clkout1@1 {
204                reg = <1>;
205                ti,clkout-fmt = <0x01>; // LVDS
206                ti,clkout-sysref;
207            };
208        };
209    };
210