1Binding for a type of quad channel digital frequency synthesizer found on 2certain STMicroelectronics consumer electronics SoC devices. 3 4This version contains a programmable PLL which can generate up to 216, 432 5or 660MHz (from a 30MHz oscillator input) as the input to the digital 6synthesizers. 7 8This binding uses the common clock binding[1]. 9 10[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 11 12Required properties: 13- compatible : shall be: 14 "st,stih416-quadfs216", "st,quadfs" 15 "st,stih416-quadfs432", "st,quadfs" 16 "st,stih416-quadfs660-E", "st,quadfs" 17 "st,stih416-quadfs660-F", "st,quadfs" 18 "st,stih407-quadfs660-C", "st,quadfs" 19 "st,stih407-quadfs660-D", "st,quadfs" 20 21 22- #clock-cells : from common clock binding; shall be set to 1. 23 24- reg : A Base address and length of the register set. 25 26- clocks : from common clock binding 27 28- clock-output-names : From common clock binding. The block has 4 29 clock outputs but not all of them in a specific instance 30 have to be used in the SoC. If a clock name is left as 31 an empty string then no clock will be created for the 32 output associated with that string index. If fewer than 33 4 strings are provided then no clocks will be created 34 for the remaining outputs. 35 36Example: 37 38 clockgen_e: clockgen-e@fd3208bc { 39 #clock-cells = <1>; 40 compatible = "st,stih416-quadfs660-E", "st,quadfs"; 41 reg = <0xfd3208bc 0xB0>; 42 43 clocks = <&clk_sysin>; 44 clock-output-names = "clk-m-pix-mdtp-0", 45 "clk-m-pix-mdtp-1", 46 "clk-m-pix-mdtp-2", 47 "clk-m-mpelpc"; 48 }; 49