xref: /linux/Documentation/devicetree/bindings/clock/st/st,flexgen.txt (revision ca55b2fef3a9373fcfc30f82fd26bc7fccbda732) 
1Binding for a type of flexgen structure found on certain
2STMicroelectronics consumer electronics SoC devices
3
4This structure includes:
5- a clock cross bar (represented by a mux element)
6- a pre and final dividers (represented by a divider and gate elements)
7
8Flexgen structure is a part of Clockgen[1].
9
10Please find an example below:
11
12    Clockgen block diagram
13    -------------------------------------------------------------------
14   |                     Flexgen structure                             |
15   |                  ---------------------------------------------    |
16   |                 |    -------       --------       --------    |   |
17clk_sysin            |   |       |     |        |     |        |   |   |
18---|-----------------|-->|       |     |        |     |        |   |   |
19   | |               |   |       |     |        |     |        |   |   |
20   | |   -------     |   |       |     |Pre     |     |Final   |   |   |
21   | |  |PLL0   |    |   |       |     |Dividers|     |Dividers|   |   |
22   | |->|       |    |   |       |     |  x32   |     |  x32   |   |   |
23   | |  |  odf_0|----|-->|       |     |        |     |        |   |   |
24   | |  |       |    |   |       |     |        |     |        |   |   |
25   | |  |       |    |   |       |     |        |     |        |   |   |
26   | |  |       |    |   |       |     |        |     |        |   |   |
27   | |  |       |    |   |       |     |        |     |        |   |   |
28   | |   -------     |   |       |     |        |     |        |   |   |
29   | |               |   |       |     |        |     |        |   |   |
30   | |   -------     |   | Clock |     |        |     |        |   |   |
31   | |  |PLL1   |    |   |       |     |        |     |        |   |   |
32   | |->|       |    |   | Cross |     |        |     |        |   |   |
33   | |  |  odf_0|----|-->|       |     |        |     |        | CLK_DIV[31:0]
34   | |  |       |    |   | Bar   |====>|        |====>|        |===|=========>
35   | |  |       |    |   |       |     |        |     |        |   |   |
36   | |  |       |    |   |       |     |        |     |        |   |   |
37   | |  |       |    |   |       |     |        |     |        |   |   |
38   | |   -------     |   |       |     |        |     |        |   |   |
39   | |               |   |       |     |        |     |        |   |   |
40   | |   -------     |   |       |     |        |     |        |   |   |
41   | |  |QUADFS |    |   |       |     |        |     |        |   |   |
42   | |->|    ch0|----|-->|       |     |        |     |        |   |   |
43   |    |       |    |   |       |     |        |     |        |   |   |
44   |    |    ch1|----|-->|       |     |        |     |        |   |   |
45   |    |       |    |   |       |     |        |     |        |   |   |
46   |    |    ch2|----|-->|       |     | DIV    |     | DIV    |   |   |
47   |    |       |    |   |       |     |  1 to  |     |  1 to  |   |   |
48   |    |    ch3|----|-->|       |     |   1024 |     |     64 |   |   |
49   |     -------     |   |       |     |        |     |        |   |   |
50   |                 |    -------       --------       --------    |   |
51   |                   --------------------------------------------    |
52   |                                                                   |
53    -------------------------------------------------------------------
54
55This binding uses the common clock binding[2].
56
57[1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
58[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
59
60Required properties:
61- compatible : shall be:
62  "st,flexgen"
63
64- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
65  outputs).
66
67- clocks : must be set to the parent's phandle. it's could be output clocks of
68  a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
69
70- clock-output-names : List of strings used to name the clock outputs.
71
72Example:
73
74	clk_s_c0_flexgen: clk-s-c0-flexgen {
75
76		#clock-cells = <1>;
77		compatible = "st,flexgen";
78
79		clocks = <&clk_s_c0_pll0 0>,
80			 <&clk_s_c0_pll1 0>,
81			 <&clk_s_c0_quadfs 0>,
82			 <&clk_s_c0_quadfs 1>,
83			 <&clk_s_c0_quadfs 2>,
84			 <&clk_s_c0_quadfs 3>,
85			 <&clk_sysin>;
86
87		clock-output-names = "clk-icn-gpu",
88				     "clk-fdma",
89				     "clk-nand",
90				     "clk-hva",
91				     "clk-proc-stfe",
92				     "clk-proc-tp",
93				     "clk-rx-icn-dmu",
94				     "clk-rx-icn-hva",
95				     "clk-icn-cpu",
96				     "clk-tx-icn-dmu",
97				     "clk-mmc-0",
98				     "clk-mmc-1",
99				     "clk-jpegdec",
100				     "clk-ext2fa9",
101				     "clk-ic-bdisp-0",
102				     "clk-ic-bdisp-1",
103				     "clk-pp-dmu",
104				     "clk-vid-dmu",
105				     "clk-dss-lpc",
106				     "clk-st231-aud-0",
107				     "clk-st231-gp-1",
108				     "clk-st231-dmu",
109				     "clk-icn-lmi",
110				     "clk-tx-icn-disp-1",
111				     "clk-icn-sbc",
112				     "clk-stfe-frc2",
113				     "clk-eth-phy",
114				     "clk-eth-ref-phyclk",
115				     "clk-flash-promip",
116				     "clk-main-disp",
117				     "clk-aux-disp",
118				     "clk-compo-dvp";
119	};
120