xref: /linux/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt (revision 0883c2c06fb5bcf5b9e008270827e63c09a88c1e) 
1Binding for a ST pll clock driver.
2
3This binding uses the common clock binding[1].
4Base address is located to the parent node. See clock binding[2]
5
6[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
7[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
8
9Required properties:
10
11- compatible : shall be:
12	"st,clkgena-prediv-c65",	"st,clkgena-prediv"
13	"st,clkgena-prediv-c32",	"st,clkgena-prediv"
14
15	"st,clkgena-plls-c65"
16	"st,plls-c32-a1x-0",		"st,clkgen-plls-c32"
17	"st,plls-c32-a1x-1",		"st,clkgen-plls-c32"
18	"st,stih415-plls-c32-a9",	"st,clkgen-plls-c32"
19	"st,stih415-plls-c32-ddr",	"st,clkgen-plls-c32"
20	"st,stih416-plls-c32-a9",	"st,clkgen-plls-c32"
21	"st,stih416-plls-c32-ddr",	"st,clkgen-plls-c32"
22	"st,stih407-plls-c32-a0",	"st,clkgen-plls-c32"
23	"st,stih407-plls-c32-a9",	"st,clkgen-plls-c32"
24	"sst,plls-c32-cx_0",		"st,clkgen-plls-c32"
25	"sst,plls-c32-cx_1",		"st,clkgen-plls-c32"
26	"st,stih418-plls-c28-a9",	"st,clkgen-plls-c32"
27
28	"st,stih415-gpu-pll-c32",	"st,clkgengpu-pll-c32"
29	"st,stih416-gpu-pll-c32",	"st,clkgengpu-pll-c32"
30
31- #clock-cells : From common clock binding; shall be set to 1.
32
33- clocks : From common clock binding
34
35- clock-output-names : From common clock binding.
36
37Example:
38
39	clockgen-a@fee62000 {
40		reg = <0xfee62000 0xb48>;
41
42		clk_s_a0_pll: clk-s-a0-pll {
43			#clock-cells = <1>;
44			compatible = "st,clkgena-plls-c65";
45
46			clocks = <&clk_sysin>;
47
48			clock-output-names = "clk-s-a0-pll0-hs",
49					     "clk-s-a0-pll0-ls",
50					     "clk-s-a0-pll1";
51		};
52	};
53