1*ef6eb322SLinus WalleijST Microelectronics Nomadik SRC System Reset and Control 2*ef6eb322SLinus Walleij 3*ef6eb322SLinus WalleijThis binding uses the common clock binding: 4*ef6eb322SLinus WalleijDocumentation/devicetree/bindings/clock/clock-bindings.txt 5*ef6eb322SLinus Walleij 6*ef6eb322SLinus WalleijThe Nomadik SRC controller is responsible of controlling chrystals, 7*ef6eb322SLinus WalleijPLLs and clock gates. 8*ef6eb322SLinus Walleij 9*ef6eb322SLinus WalleijRequired properties for the SRC node: 10*ef6eb322SLinus Walleij- compatible: must be "stericsson,nomadik-src" 11*ef6eb322SLinus Walleij- reg: must contain the SRC register base and size 12*ef6eb322SLinus Walleij 13*ef6eb322SLinus WalleijOptional properties for the SRC node: 14*ef6eb322SLinus Walleij- disable-sxtalo: if present this will disable the SXTALO 15*ef6eb322SLinus Walleij i.e. the driver output for the slow 32kHz chrystal, if the 16*ef6eb322SLinus Walleij board has its own circuitry for providing this oscillator 17*ef6eb322SLinus Walleij- disable-mxtal: if present this will disable the MXTALO, 18*ef6eb322SLinus Walleij i.e. the driver output for the main (~19.2 MHz) chrystal, 19*ef6eb322SLinus Walleij if the board has its own circuitry for providing this 20*ef6eb322SLinus Walleij osciallator 21*ef6eb322SLinus Walleij 22*ef6eb322SLinus Walleij 23*ef6eb322SLinus WalleijPLL nodes: these nodes represent the two PLLs on the system, 24*ef6eb322SLinus Walleijwhich should both have the main chrystal, represented as a 25*ef6eb322SLinus Walleijfixed frequency clock, as parent. 26*ef6eb322SLinus Walleij 27*ef6eb322SLinus WalleijRequired properties for the two PLL nodes: 28*ef6eb322SLinus Walleij- compatible: must be "st,nomadik-pll-clock" 29*ef6eb322SLinus Walleij- clock-cells: must be 0 30*ef6eb322SLinus Walleij- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively 31*ef6eb322SLinus Walleij- clocks: this clock will have main chrystal as parent 32*ef6eb322SLinus Walleij 33*ef6eb322SLinus Walleij 34*ef6eb322SLinus WalleijHCLK nodes: these represent the clock gates on individual 35*ef6eb322SLinus Walleijlines from the HCLK clock tree and the gate for individual 36*ef6eb322SLinus Walleijlines from the PCLK clock tree. 37*ef6eb322SLinus Walleij 38*ef6eb322SLinus WalleijRequires properties for the HCLK nodes: 39*ef6eb322SLinus Walleij- compatible: must be "st,nomadik-hclk-clock" 40*ef6eb322SLinus Walleij- clock-cells: must be 0 41*ef6eb322SLinus Walleij- clock-id: must be the clock ID from 0 to 63 according to 42*ef6eb322SLinus Walleij this table: 43*ef6eb322SLinus Walleij 44*ef6eb322SLinus Walleij 0: HCLKDMA0 45*ef6eb322SLinus Walleij 1: HCLKSMC 46*ef6eb322SLinus Walleij 2: HCLKSDRAM 47*ef6eb322SLinus Walleij 3: HCLKDMA1 48*ef6eb322SLinus Walleij 4: HCLKCLCD 49*ef6eb322SLinus Walleij 5: PCLKIRDA 50*ef6eb322SLinus Walleij 6: PCLKSSP 51*ef6eb322SLinus Walleij 7: PCLKUART0 52*ef6eb322SLinus Walleij 8: PCLKSDI 53*ef6eb322SLinus Walleij 9: PCLKI2C0 54*ef6eb322SLinus Walleij 10: PCLKI2C1 55*ef6eb322SLinus Walleij 11: PCLKUART1 56*ef6eb322SLinus Walleij 12: PCLMSP0 57*ef6eb322SLinus Walleij 13: HCLKUSB 58*ef6eb322SLinus Walleij 14: HCLKDIF 59*ef6eb322SLinus Walleij 15: HCLKSAA 60*ef6eb322SLinus Walleij 16: HCLKSVA 61*ef6eb322SLinus Walleij 17: PCLKHSI 62*ef6eb322SLinus Walleij 18: PCLKXTI 63*ef6eb322SLinus Walleij 19: PCLKUART2 64*ef6eb322SLinus Walleij 20: PCLKMSP1 65*ef6eb322SLinus Walleij 21: PCLKMSP2 66*ef6eb322SLinus Walleij 22: PCLKOWM 67*ef6eb322SLinus Walleij 23: HCLKHPI 68*ef6eb322SLinus Walleij 24: PCLKSKE 69*ef6eb322SLinus Walleij 25: PCLKHSEM 70*ef6eb322SLinus Walleij 26: HCLK3D 71*ef6eb322SLinus Walleij 27: HCLKHASH 72*ef6eb322SLinus Walleij 28: HCLKCRYP 73*ef6eb322SLinus Walleij 29: PCLKMSHC 74*ef6eb322SLinus Walleij 30: HCLKUSBM 75*ef6eb322SLinus Walleij 31: HCLKRNG 76*ef6eb322SLinus Walleij (32, 33, 34, 35 RESERVED) 77*ef6eb322SLinus Walleij 36: CLDCLK 78*ef6eb322SLinus Walleij 37: IRDACLK 79*ef6eb322SLinus Walleij 38: SSPICLK 80*ef6eb322SLinus Walleij 39: UART0CLK 81*ef6eb322SLinus Walleij 40: SDICLK 82*ef6eb322SLinus Walleij 41: I2C0CLK 83*ef6eb322SLinus Walleij 42: I2C1CLK 84*ef6eb322SLinus Walleij 43: UART1CLK 85*ef6eb322SLinus Walleij 44: MSPCLK0 86*ef6eb322SLinus Walleij 45: USBCLK 87*ef6eb322SLinus Walleij 46: DIFCLK 88*ef6eb322SLinus Walleij 47: IPI2CCLK 89*ef6eb322SLinus Walleij 48: IPBMCCLK 90*ef6eb322SLinus Walleij 49: HSICLKRX 91*ef6eb322SLinus Walleij 50: HSICLKTX 92*ef6eb322SLinus Walleij 51: UART2CLK 93*ef6eb322SLinus Walleij 52: MSPCLK1 94*ef6eb322SLinus Walleij 53: MSPCLK2 95*ef6eb322SLinus Walleij 54: OWMCLK 96*ef6eb322SLinus Walleij (55 RESERVED) 97*ef6eb322SLinus Walleij 56: SKECLK 98*ef6eb322SLinus Walleij (57 RESERVED) 99*ef6eb322SLinus Walleij 58: 3DCLK 100*ef6eb322SLinus Walleij 59: PCLKMSP3 101*ef6eb322SLinus Walleij 60: MSPCLK3 102*ef6eb322SLinus Walleij 61: MSHCCLK 103*ef6eb322SLinus Walleij 62: USBMCLK 104*ef6eb322SLinus Walleij 63: RNGCCLK 105