xref: /linux/Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml (revision 55d0969c451159cff86949b38c39171cab962069) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Sophgo SG2042 Clock Generator for divider/mux/gate
8
9maintainers:
10  - Chen Wang <unicorn_wang@outlook.com>
11
12properties:
13  compatible:
14    const: sophgo,sg2042-clkgen
15
16  reg:
17    maxItems: 1
18
19  clocks:
20    items:
21      - description: Main PLL
22      - description: Fixed PLL
23      - description: DDR PLL 0
24      - description: DDR PLL 1
25
26  clock-names:
27    items:
28      - const: mpll
29      - const: fpll
30      - const: dpll0
31      - const: dpll1
32
33  '#clock-cells':
34    const: 1
35    description:
36      See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices.
37
38required:
39  - compatible
40  - reg
41  - clocks
42  - clock-names
43  - '#clock-cells'
44
45additionalProperties: false
46
47examples:
48  - |
49    clock-controller@30012000 {
50      compatible = "sophgo,sg2042-clkgen";
51      reg = <0x30012000 0x1000>;
52      clocks = <&pllclk 0>,
53               <&pllclk 1>,
54               <&pllclk 2>,
55               <&pllclk 3>;
56      clock-names = "mpll",
57                    "fpll",
58                    "dpll0",
59                    "dpll1";
60      #clock-cells = <1>;
61    };
62