1Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable 2i2c clock generator. 3 4Reference 5[1] Si5341 Data Sheet 6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf 7[2] Si5341 Reference Manual 8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf 9[3] Si5345 Reference Manual 10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf 11 12The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output 13clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which 14in turn can be directed to any of the 10 (or 4) outputs through a divider. 15The internal structure of the clock generators can be found in [2]. 16The Si5345 is similar to the Si5341 with the addition of fractional input 17dividers and automatic input selection, as described in [3]. 18The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs. 19 20The driver can be used in "as is" mode, reading the current settings from the 21chip at boot, in case you have a (pre-)programmed device. If the PLL is not 22configured when the driver probes, it assumes the driver must fully initialize 23it. 24 25The device type, speed grade and revision are determined runtime by probing. 26 27The driver currently only supports XTAL input mode, and does not support any 28fancy input configurations. They can still be programmed into the chip and 29the driver will leave them "as is". 30 31==I2C device node== 32 33Required properties: 34- compatible: shall be one of the following: 35 "silabs,si5340" - Si5340 A/B/C/D 36 "silabs,si5341" - Si5341 A/B/C/D 37 "silabs,si5342" - Si5342 A/B/C/D 38 "silabs,si5344" - Si5344 A/B/C/D 39 "silabs,si5345" - Si5345 A/B/C/D 40- reg: i2c device address, usually 0x74 41- #clock-cells: from common clock binding; shall be set to 2. 42 The first value is "0" for outputs, "1" for synthesizers. 43 The second value is the output or synthesizer index. 44- clocks: from common clock binding; list of parent clock handles, 45 corresponding to inputs. Use a fixed clock for the "xtal" input. 46 At least one must be present. 47- clock-names: One of: "xtal", "in0", "in1", "in2" 48- vdd-supply: Regulator node for VDD 49 50Optional properties: 51- vdda-supply: Regulator node for VDDA 52- vdds-supply: Regulator node for VDDS 53- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL 54 feedback divider. Must be such that the PLL output is in the valid range. For 55 example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only 56 the fraction matters, using 3500 and 12 will deliver the exact same result. 57 If these are not specified, and the PLL is not yet programmed when the driver 58 probes, the PLL will be set to 14GHz. 59- silabs,reprogram: When present, the driver will always assume the device must 60 be initialized, and always performs the soft-reset routine. Since this will 61 temporarily stop all output clocks, don't do this if the chip is generating 62 the CPU clock for example. 63- interrupts: Interrupt for INTRb pin. 64- #address-cells: shall be set to 1. 65- #size-cells: shall be set to 0. 66 67 68== Child nodes: Outputs == 69 70The child nodes list the output clocks. 71 72Each of the clock outputs can be overwritten individually by using a child node. 73If a child node for a clock output is not set, the configuration remains 74unchanged. 75 76Required child node properties: 77- reg: number of clock output. 78 79Optional child node properties: 80- vdd-supply: Regulator node for VDD for this output. The driver selects default 81 values for common-mode and amplitude based on the voltage. 82- silabs,format: Output format, one of: 83 1 = differential (defaults to LVDS levels) 84 2 = low-power (defaults to HCSL levels) 85 4 = LVCMOS 86- silabs,common-mode: Manually override output common mode, see [2] for values 87- silabs,amplitude: Manually override output amplitude, see [2] for values 88- silabs,synth-master: boolean. If present, this output is allowed to change the 89 multisynth frequency dynamically. 90- silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH 91 when disabled, otherwise it's driven LOW. 92 93==Example== 94 95/* 48MHz reference crystal */ 96ref48: ref48M { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <48000000>; 100}; 101 102i2c-master-node { 103 /* Programmable clock (for logic) */ 104 si5341: clock-generator@74 { 105 reg = <0x74>; 106 compatible = "silabs,si5341"; 107 #clock-cells = <2>; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 clocks = <&ref48>; 111 clock-names = "xtal"; 112 113 silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */ 114 silabs,pll-m-den = <48>; 115 silabs,reprogram; /* Chips are not programmed, always reset */ 116 117 out@0 { 118 reg = <0>; 119 silabs,format = <1>; /* LVDS 3v3 */ 120 silabs,common-mode = <3>; 121 silabs,amplitude = <3>; 122 silabs,synth-master; 123 }; 124 125 /* 126 * Output 6 configuration: 127 * LVDS 1v8 128 */ 129 out@6 { 130 reg = <6>; 131 silabs,format = <1>; /* LVDS 1v8 */ 132 silabs,common-mode = <13>; 133 silabs,amplitude = <3>; 134 }; 135 136 /* 137 * Output 8 configuration: 138 * HCSL 3v3 139 */ 140 out@8 { 141 reg = <8>; 142 silabs,format = <2>; 143 silabs,common-mode = <11>; 144 silabs,amplitude = <3>; 145 }; 146 }; 147}; 148 149some-video-node { 150 /* Standard clock bindings */ 151 clock-names = "pixel"; 152 clocks = <&si5341 0 7>; /* Output 7 */ 153 154 /* Set output 7 to use syntesizer 3 as its parent */ 155 assigned-clocks = <&si5341 0 7>, <&si5341 1 3>; 156 assigned-clock-parents = <&si5341 1 3>; 157 /* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */ 158 assigned-clock-rates = <148500000>, <594000000>; 159}; 160 161some-audio-node { 162 clock-names = "i2s-clk"; 163 clocks = <&si5341 0 0>; 164 /* 165 * since output 0 is a synth-master, the synth will be automatically set 166 * to an appropriate frequency when the audio driver requests another 167 * frequency. We give control over synth 2 to this output here. 168 */ 169 assigned-clocks = <&si5341 0 0>; 170 assigned-clock-parents = <&si5341 1 2>; 171}; 172