xref: /linux/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml (revision fb4b06f521c1cdf04088151ed587c188862e3111) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
9
10maintainers:
11  - Paul Walmsley  <paul.walmsley@sifive.com>
12
13description:
14  On the FU540 family of SoCs, most system-wide clock and reset integration
15  is via the PRCI IP block.
16  The clock consumer should specify the desired clock via the clock ID
17  macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
18  These macros begin with PRCI_CLK_.
19
20  The hfclk and rtcclk nodes are required, and represent physical
21  crystals or resonators located on the PCB.  These nodes should be present
22  underneath /, rather than /soc.
23
24properties:
25  compatible:
26    const: sifive,fu540-c000-prci
27
28  reg:
29    maxItems: 1
30
31  clocks:
32    items:
33      - description: high frequency clock.
34      - description: RTL clock.
35
36  clock-names:
37    items:
38      - const: hfclk
39      - const: rtcclk
40
41  "#clock-cells":
42    const: 1
43
44required:
45  - compatible
46  - reg
47  - clocks
48  - "#clock-cells"
49
50additionalProperties: false
51
52examples:
53  - |
54    prci: clock-controller@10000000 {
55      compatible = "sifive,fu540-c000-prci";
56      reg = <0x10000000 0x1000>;
57      clocks = <&hfclk>, <&rtcclk>;
58      #clock-cells = <1>;
59    };
60