xref: /linux/Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml (revision 24bce201d79807b668bf9d9e0aca801c5c0d5f78) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos7885 SoC clock controller
8
9maintainers:
10  - Dávid Virág <virag.david003@gmail.com>
11  - Chanwoo Choi <cw00.choi@samsung.com>
12  - Krzysztof Kozlowski <krzk@kernel.org>
13  - Sylwester Nawrocki <s.nawrocki@samsung.com>
14  - Tomasz Figa <tomasz.figa@gmail.com>
15
16description: |
17  Exynos7885 clock controller is comprised of several CMU units, generating
18  clocks for different domains. Those CMU units are modeled as separate device
19  tree nodes, and might depend on each other. The root clock in that root tree
20  is an external clock: OSCCLK (26 MHz). This external clock must be defined
21  as a fixed-rate clock in dts.
22
23  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
24  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
25
26  Each clock is assigned an identifier and client nodes can use this identifier
27  to specify the clock which they consume. All clocks available for usage
28  in clock consumer nodes are defined as preprocessor macros in
29  'dt-bindings/clock/exynos7885.h' header.
30
31properties:
32  compatible:
33    enum:
34      - samsung,exynos7885-cmu-top
35      - samsung,exynos7885-cmu-core
36      - samsung,exynos7885-cmu-peri
37
38  clocks:
39    minItems: 1
40    maxItems: 10
41
42  clock-names:
43    minItems: 1
44    maxItems: 10
45
46  "#clock-cells":
47    const: 1
48
49  reg:
50    maxItems: 1
51
52allOf:
53  - if:
54      properties:
55        compatible:
56          contains:
57            const: samsung,exynos7885-cmu-top
58
59    then:
60      properties:
61        clocks:
62          items:
63            - description: External reference clock (26 MHz)
64
65        clock-names:
66          items:
67            - const: oscclk
68
69  - if:
70      properties:
71        compatible:
72          contains:
73            const: samsung,exynos7885-cmu-core
74
75    then:
76      properties:
77        clocks:
78          items:
79            - description: External reference clock (26 MHz)
80            - description: CMU_CORE bus clock (from CMU_TOP)
81            - description: CCI clock (from CMU_TOP)
82            - description: G3D clock (from CMU_TOP)
83
84        clock-names:
85          items:
86            - const: oscclk
87            - const: dout_core_bus
88            - const: dout_core_cci
89            - const: dout_core_g3d
90
91  - if:
92      properties:
93        compatible:
94          contains:
95            const: samsung,exynos7885-cmu-peri
96
97    then:
98      properties:
99        clocks:
100          items:
101            - description: External reference clock (26 MHz)
102            - description: CMU_PERI bus clock (from CMU_TOP)
103            - description: SPI0 clock (from CMU_TOP)
104            - description: SPI1 clock (from CMU_TOP)
105            - description: UART0 clock (from CMU_TOP)
106            - description: UART1 clock (from CMU_TOP)
107            - description: UART2 clock (from CMU_TOP)
108            - description: USI0 clock (from CMU_TOP)
109            - description: USI1 clock (from CMU_TOP)
110            - description: USI2 clock (from CMU_TOP)
111
112        clock-names:
113          items:
114            - const: oscclk
115            - const: dout_peri_bus
116            - const: dout_peri_spi0
117            - const: dout_peri_spi1
118            - const: dout_peri_uart0
119            - const: dout_peri_uart1
120            - const: dout_peri_uart2
121            - const: dout_peri_usi0
122            - const: dout_peri_usi1
123            - const: dout_peri_usi2
124
125required:
126  - compatible
127  - "#clock-cells"
128  - clocks
129  - clock-names
130  - reg
131
132additionalProperties: false
133
134examples:
135  # Clock controller node for CMU_PERI
136  - |
137    #include <dt-bindings/clock/exynos7885.h>
138
139    cmu_peri: clock-controller@10010000 {
140        compatible = "samsung,exynos7885-cmu-peri";
141        reg = <0x10010000 0x8000>;
142        #clock-cells = <1>;
143
144        clocks = <&oscclk>,
145                 <&cmu_top CLK_DOUT_PERI_BUS>,
146                 <&cmu_top CLK_DOUT_PERI_SPI0>,
147                 <&cmu_top CLK_DOUT_PERI_SPI1>,
148                 <&cmu_top CLK_DOUT_PERI_UART0>,
149                 <&cmu_top CLK_DOUT_PERI_UART1>,
150                 <&cmu_top CLK_DOUT_PERI_UART2>,
151                 <&cmu_top CLK_DOUT_PERI_USI0>,
152                 <&cmu_top CLK_DOUT_PERI_USI1>,
153                 <&cmu_top CLK_DOUT_PERI_USI2>;
154        clock-names = "oscclk",
155                      "dout_peri_bus",
156                      "dout_peri_spi0",
157                      "dout_peri_spi1",
158                      "dout_peri_uart0",
159                      "dout_peri_uart1",
160                      "dout_peri_uart2",
161                      "dout_peri_usi0",
162                      "dout_peri_usi1",
163                      "dout_peri_usi2";
164    };
165
166...
167