177624aa1SDavid Virag# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 277624aa1SDavid Virag%YAML 1.2 377624aa1SDavid Virag--- 477624aa1SDavid Virag$id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml# 577624aa1SDavid Virag$schema: http://devicetree.org/meta-schemas/core.yaml# 677624aa1SDavid Virag 777624aa1SDavid Viragtitle: Samsung Exynos7885 SoC clock controller 877624aa1SDavid Virag 977624aa1SDavid Viragmaintainers: 1077624aa1SDavid Virag - Dávid Virág <virag.david003@gmail.com> 1177624aa1SDavid Virag - Chanwoo Choi <cw00.choi@samsung.com> 128a1e6bb3SKrzysztof Kozlowski - Krzysztof Kozlowski <krzk@kernel.org> 1377624aa1SDavid Virag - Sylwester Nawrocki <s.nawrocki@samsung.com> 1477624aa1SDavid Virag - Tomasz Figa <tomasz.figa@gmail.com> 1577624aa1SDavid Virag 1677624aa1SDavid Viragdescription: | 1777624aa1SDavid Virag Exynos7885 clock controller is comprised of several CMU units, generating 1877624aa1SDavid Virag clocks for different domains. Those CMU units are modeled as separate device 1977624aa1SDavid Virag tree nodes, and might depend on each other. The root clock in that root tree 2077624aa1SDavid Virag is an external clock: OSCCLK (26 MHz). This external clock must be defined 2177624aa1SDavid Virag as a fixed-rate clock in dts. 2277624aa1SDavid Virag 2377624aa1SDavid Virag CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and 2477624aa1SDavid Virag dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. 2577624aa1SDavid Virag 2677624aa1SDavid Virag Each clock is assigned an identifier and client nodes can use this identifier 2777624aa1SDavid Virag to specify the clock which they consume. All clocks available for usage 2877624aa1SDavid Virag in clock consumer nodes are defined as preprocessor macros in 2977624aa1SDavid Virag 'dt-bindings/clock/exynos7885.h' header. 3077624aa1SDavid Virag 3177624aa1SDavid Viragproperties: 3277624aa1SDavid Virag compatible: 3377624aa1SDavid Virag enum: 3477624aa1SDavid Virag - samsung,exynos7885-cmu-top 3577624aa1SDavid Virag - samsung,exynos7885-cmu-core 36*cd268e30SDavid Virag - samsung,exynos7885-cmu-fsys 3777624aa1SDavid Virag - samsung,exynos7885-cmu-peri 3877624aa1SDavid Virag 3977624aa1SDavid Virag clocks: 4077624aa1SDavid Virag minItems: 1 4177624aa1SDavid Virag maxItems: 10 4277624aa1SDavid Virag 4377624aa1SDavid Virag clock-names: 4477624aa1SDavid Virag minItems: 1 4577624aa1SDavid Virag maxItems: 10 4677624aa1SDavid Virag 4777624aa1SDavid Virag "#clock-cells": 4877624aa1SDavid Virag const: 1 4977624aa1SDavid Virag 5077624aa1SDavid Virag reg: 5177624aa1SDavid Virag maxItems: 1 5277624aa1SDavid Virag 5377624aa1SDavid ViragallOf: 5477624aa1SDavid Virag - if: 5577624aa1SDavid Virag properties: 5677624aa1SDavid Virag compatible: 5777624aa1SDavid Virag contains: 5877624aa1SDavid Virag const: samsung,exynos7885-cmu-top 5977624aa1SDavid Virag 6077624aa1SDavid Virag then: 6177624aa1SDavid Virag properties: 6277624aa1SDavid Virag clocks: 6377624aa1SDavid Virag items: 6477624aa1SDavid Virag - description: External reference clock (26 MHz) 6577624aa1SDavid Virag 6677624aa1SDavid Virag clock-names: 6777624aa1SDavid Virag items: 6877624aa1SDavid Virag - const: oscclk 6977624aa1SDavid Virag 7077624aa1SDavid Virag - if: 7177624aa1SDavid Virag properties: 7277624aa1SDavid Virag compatible: 7377624aa1SDavid Virag contains: 7477624aa1SDavid Virag const: samsung,exynos7885-cmu-core 7577624aa1SDavid Virag 7677624aa1SDavid Virag then: 7777624aa1SDavid Virag properties: 7877624aa1SDavid Virag clocks: 7977624aa1SDavid Virag items: 8077624aa1SDavid Virag - description: External reference clock (26 MHz) 8177624aa1SDavid Virag - description: CMU_CORE bus clock (from CMU_TOP) 8277624aa1SDavid Virag - description: CCI clock (from CMU_TOP) 8377624aa1SDavid Virag - description: G3D clock (from CMU_TOP) 8477624aa1SDavid Virag 8577624aa1SDavid Virag clock-names: 8677624aa1SDavid Virag items: 8777624aa1SDavid Virag - const: oscclk 8877624aa1SDavid Virag - const: dout_core_bus 8977624aa1SDavid Virag - const: dout_core_cci 9077624aa1SDavid Virag - const: dout_core_g3d 9177624aa1SDavid Virag 9277624aa1SDavid Virag - if: 9377624aa1SDavid Virag properties: 9477624aa1SDavid Virag compatible: 9577624aa1SDavid Virag contains: 96*cd268e30SDavid Virag const: samsung,exynos7885-cmu-fsys 97*cd268e30SDavid Virag 98*cd268e30SDavid Virag then: 99*cd268e30SDavid Virag properties: 100*cd268e30SDavid Virag clocks: 101*cd268e30SDavid Virag items: 102*cd268e30SDavid Virag - description: External reference clock (26 MHz) 103*cd268e30SDavid Virag - description: CMU_FSYS bus clock (from CMU_TOP) 104*cd268e30SDavid Virag - description: MMC_CARD clock (from CMU_TOP) 105*cd268e30SDavid Virag - description: MMC_EMBD clock (from CMU_TOP) 106*cd268e30SDavid Virag - description: MMC_SDIO clock (from CMU_TOP) 107*cd268e30SDavid Virag - description: USB30DRD clock (from CMU_TOP) 108*cd268e30SDavid Virag 109*cd268e30SDavid Virag clock-names: 110*cd268e30SDavid Virag items: 111*cd268e30SDavid Virag - const: oscclk 112*cd268e30SDavid Virag - const: dout_fsys_bus 113*cd268e30SDavid Virag - const: dout_fsys_mmc_card 114*cd268e30SDavid Virag - const: dout_fsys_mmc_embd 115*cd268e30SDavid Virag - const: dout_fsys_mmc_sdio 116*cd268e30SDavid Virag - const: dout_fsys_usb30drd 117*cd268e30SDavid Virag 118*cd268e30SDavid Virag - if: 119*cd268e30SDavid Virag properties: 120*cd268e30SDavid Virag compatible: 121*cd268e30SDavid Virag contains: 12277624aa1SDavid Virag const: samsung,exynos7885-cmu-peri 12377624aa1SDavid Virag 12477624aa1SDavid Virag then: 12577624aa1SDavid Virag properties: 12677624aa1SDavid Virag clocks: 12777624aa1SDavid Virag items: 12877624aa1SDavid Virag - description: External reference clock (26 MHz) 12977624aa1SDavid Virag - description: CMU_PERI bus clock (from CMU_TOP) 13077624aa1SDavid Virag - description: SPI0 clock (from CMU_TOP) 13177624aa1SDavid Virag - description: SPI1 clock (from CMU_TOP) 13277624aa1SDavid Virag - description: UART0 clock (from CMU_TOP) 13377624aa1SDavid Virag - description: UART1 clock (from CMU_TOP) 13477624aa1SDavid Virag - description: UART2 clock (from CMU_TOP) 13577624aa1SDavid Virag - description: USI0 clock (from CMU_TOP) 13677624aa1SDavid Virag - description: USI1 clock (from CMU_TOP) 13777624aa1SDavid Virag - description: USI2 clock (from CMU_TOP) 13877624aa1SDavid Virag 13977624aa1SDavid Virag clock-names: 14077624aa1SDavid Virag items: 14177624aa1SDavid Virag - const: oscclk 14277624aa1SDavid Virag - const: dout_peri_bus 14377624aa1SDavid Virag - const: dout_peri_spi0 14477624aa1SDavid Virag - const: dout_peri_spi1 14577624aa1SDavid Virag - const: dout_peri_uart0 14677624aa1SDavid Virag - const: dout_peri_uart1 14777624aa1SDavid Virag - const: dout_peri_uart2 14877624aa1SDavid Virag - const: dout_peri_usi0 14977624aa1SDavid Virag - const: dout_peri_usi1 15077624aa1SDavid Virag - const: dout_peri_usi2 15177624aa1SDavid Virag 15277624aa1SDavid Viragrequired: 15377624aa1SDavid Virag - compatible 15477624aa1SDavid Virag - "#clock-cells" 15577624aa1SDavid Virag - clocks 15677624aa1SDavid Virag - clock-names 15777624aa1SDavid Virag - reg 15877624aa1SDavid Virag 15977624aa1SDavid ViragadditionalProperties: false 16077624aa1SDavid Virag 16177624aa1SDavid Viragexamples: 16277624aa1SDavid Virag # Clock controller node for CMU_PERI 16377624aa1SDavid Virag - | 16477624aa1SDavid Virag #include <dt-bindings/clock/exynos7885.h> 16577624aa1SDavid Virag 16677624aa1SDavid Virag cmu_peri: clock-controller@10010000 { 16777624aa1SDavid Virag compatible = "samsung,exynos7885-cmu-peri"; 16877624aa1SDavid Virag reg = <0x10010000 0x8000>; 16977624aa1SDavid Virag #clock-cells = <1>; 17077624aa1SDavid Virag 17177624aa1SDavid Virag clocks = <&oscclk>, 17277624aa1SDavid Virag <&cmu_top CLK_DOUT_PERI_BUS>, 17377624aa1SDavid Virag <&cmu_top CLK_DOUT_PERI_SPI0>, 17477624aa1SDavid Virag <&cmu_top CLK_DOUT_PERI_SPI1>, 17577624aa1SDavid Virag <&cmu_top CLK_DOUT_PERI_UART0>, 17677624aa1SDavid Virag <&cmu_top CLK_DOUT_PERI_UART1>, 17777624aa1SDavid Virag <&cmu_top CLK_DOUT_PERI_UART2>, 17877624aa1SDavid Virag <&cmu_top CLK_DOUT_PERI_USI0>, 17977624aa1SDavid Virag <&cmu_top CLK_DOUT_PERI_USI1>, 18077624aa1SDavid Virag <&cmu_top CLK_DOUT_PERI_USI2>; 18177624aa1SDavid Virag clock-names = "oscclk", 18277624aa1SDavid Virag "dout_peri_bus", 18377624aa1SDavid Virag "dout_peri_spi0", 18477624aa1SDavid Virag "dout_peri_spi1", 18577624aa1SDavid Virag "dout_peri_uart0", 18677624aa1SDavid Virag "dout_peri_uart1", 18777624aa1SDavid Virag "dout_peri_uart2", 18877624aa1SDavid Virag "dout_peri_usi0", 18977624aa1SDavid Virag "dout_peri_usi1", 19077624aa1SDavid Virag "dout_peri_usi2"; 19177624aa1SDavid Virag }; 19277624aa1SDavid Virag 19377624aa1SDavid Virag... 194