1*d0d9a962SElaine Zhang# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*d0d9a962SElaine Zhang%YAML 1.2 3*d0d9a962SElaine Zhang--- 4*d0d9a962SElaine Zhang$id: http://devicetree.org/schemas/clock/rockchip,rv1126b-cru.yaml# 5*d0d9a962SElaine Zhang$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d0d9a962SElaine Zhang 7*d0d9a962SElaine Zhangtitle: Rockchip RV1126B Clock and Reset Unit 8*d0d9a962SElaine Zhang 9*d0d9a962SElaine Zhangmaintainers: 10*d0d9a962SElaine Zhang - Elaine Zhang <zhangqing@rock-chips.com> 11*d0d9a962SElaine Zhang - Heiko Stuebner <heiko@sntech.de> 12*d0d9a962SElaine Zhang 13*d0d9a962SElaine Zhangdescription: 14*d0d9a962SElaine Zhang The rv1126b clock controller generates the clock and also implements a 15*d0d9a962SElaine Zhang reset controller for SoC peripherals. 16*d0d9a962SElaine Zhang 17*d0d9a962SElaine Zhangproperties: 18*d0d9a962SElaine Zhang compatible: 19*d0d9a962SElaine Zhang enum: 20*d0d9a962SElaine Zhang - rockchip,rv1126b-cru 21*d0d9a962SElaine Zhang 22*d0d9a962SElaine Zhang reg: 23*d0d9a962SElaine Zhang maxItems: 1 24*d0d9a962SElaine Zhang 25*d0d9a962SElaine Zhang "#clock-cells": 26*d0d9a962SElaine Zhang const: 1 27*d0d9a962SElaine Zhang 28*d0d9a962SElaine Zhang "#reset-cells": 29*d0d9a962SElaine Zhang const: 1 30*d0d9a962SElaine Zhang 31*d0d9a962SElaine Zhang clocks: 32*d0d9a962SElaine Zhang maxItems: 1 33*d0d9a962SElaine Zhang 34*d0d9a962SElaine Zhang clock-names: 35*d0d9a962SElaine Zhang const: xin24m 36*d0d9a962SElaine Zhang 37*d0d9a962SElaine Zhangrequired: 38*d0d9a962SElaine Zhang - compatible 39*d0d9a962SElaine Zhang - reg 40*d0d9a962SElaine Zhang - "#clock-cells" 41*d0d9a962SElaine Zhang - "#reset-cells" 42*d0d9a962SElaine Zhang 43*d0d9a962SElaine ZhangadditionalProperties: false 44*d0d9a962SElaine Zhang 45*d0d9a962SElaine Zhangexamples: 46*d0d9a962SElaine Zhang - | 47*d0d9a962SElaine Zhang clock-controller@20000000 { 48*d0d9a962SElaine Zhang compatible = "rockchip,rv1126b-cru"; 49*d0d9a962SElaine Zhang reg = <0x20000000 0xc0000>; 50*d0d9a962SElaine Zhang #clock-cells = <1>; 51*d0d9a962SElaine Zhang #reset-cells = <1>; 52*d0d9a962SElaine Zhang }; 53