xref: /linux/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml (revision a4eb44a6435d6d8f9e642407a4a06f65eb90ca04) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/rockchip,rk3568-cru.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ROCKCHIP rk3568 Family Clock Control Module Binding
8
9maintainers:
10  - Elaine Zhang <zhangqing@rock-chips.com>
11  - Heiko Stuebner <heiko@sntech.de>
12
13description: |
14  The RK3568 clock controller generates the clock and also implements a
15  reset controller for SoC peripherals.
16  (examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for UART module)
17  Each clock is assigned an identifier and client nodes can use this identifier
18  to specify the clock which they consume. All available clocks are defined as
19  preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
20  used in device tree sources.
21
22properties:
23  compatible:
24    enum:
25      - rockchip,rk3568-cru
26      - rockchip,rk3568-pmucru
27
28  reg:
29    maxItems: 1
30
31  "#clock-cells":
32    const: 1
33
34  "#reset-cells":
35    const: 1
36
37required:
38  - compatible
39  - reg
40  - "#clock-cells"
41  - "#reset-cells"
42
43additionalProperties: false
44
45examples:
46  # Clock Control Module node:
47  - |
48    pmucru: clock-controller@fdd00000 {
49      compatible = "rockchip,rk3568-pmucru";
50      reg = <0xfdd00000 0x1000>;
51      #clock-cells = <1>;
52      #reset-cells = <1>;
53    };
54  - |
55    cru: clock-controller@fdd20000 {
56      compatible = "rockchip,rk3568-cru";
57      reg = <0xfdd20000 0x1000>;
58      #clock-cells = <1>;
59      #reset-cells = <1>;
60    };
61