1*5b0c9b98SJohan Jonker# SPDX-License-Identifier: GPL-2.0 2*5b0c9b98SJohan Jonker%YAML 1.2 3*5b0c9b98SJohan Jonker--- 4*5b0c9b98SJohan Jonker$id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml# 5*5b0c9b98SJohan Jonker$schema: http://devicetree.org/meta-schemas/core.yaml# 6*5b0c9b98SJohan Jonker 7*5b0c9b98SJohan Jonkertitle: Rockchip RK3228 Clock and Reset Unit (CRU) 8*5b0c9b98SJohan Jonker 9*5b0c9b98SJohan Jonkermaintainers: 10*5b0c9b98SJohan Jonker - Elaine Zhang <zhangqing@rock-chips.com> 11*5b0c9b98SJohan Jonker - Heiko Stuebner <heiko@sntech.de> 12*5b0c9b98SJohan Jonker 13*5b0c9b98SJohan Jonkerdescription: | 14*5b0c9b98SJohan Jonker The RK3228 clock controller generates and supplies clocks to various 15*5b0c9b98SJohan Jonker controllers within the SoC and also implements a reset controller for SoC 16*5b0c9b98SJohan Jonker peripherals. 17*5b0c9b98SJohan Jonker Each clock is assigned an identifier and client nodes can use this identifier 18*5b0c9b98SJohan Jonker to specify the clock which they consume. All available clocks are defined as 19*5b0c9b98SJohan Jonker preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be 20*5b0c9b98SJohan Jonker used in device tree sources. Similar macros exist for the reset sources in 21*5b0c9b98SJohan Jonker these files. 22*5b0c9b98SJohan Jonker There are several clocks that are generated outside the SoC. It is expected 23*5b0c9b98SJohan Jonker that they are defined using standard clock bindings with following 24*5b0c9b98SJohan Jonker clock-output-names: 25*5b0c9b98SJohan Jonker - "xin24m" - crystal input - required 26*5b0c9b98SJohan Jonker - "ext_i2s" - external I2S clock - optional 27*5b0c9b98SJohan Jonker - "ext_gmac" - external GMAC clock - optional 28*5b0c9b98SJohan Jonker - "ext_hsadc" - external HSADC clock - optional 29*5b0c9b98SJohan Jonker - "phy_50m_out" - output clock of the pll in the mac phy 30*5b0c9b98SJohan Jonker 31*5b0c9b98SJohan Jonkerproperties: 32*5b0c9b98SJohan Jonker compatible: 33*5b0c9b98SJohan Jonker enum: 34*5b0c9b98SJohan Jonker - rockchip,rk3228-cru 35*5b0c9b98SJohan Jonker 36*5b0c9b98SJohan Jonker reg: 37*5b0c9b98SJohan Jonker maxItems: 1 38*5b0c9b98SJohan Jonker 39*5b0c9b98SJohan Jonker "#clock-cells": 40*5b0c9b98SJohan Jonker const: 1 41*5b0c9b98SJohan Jonker 42*5b0c9b98SJohan Jonker "#reset-cells": 43*5b0c9b98SJohan Jonker const: 1 44*5b0c9b98SJohan Jonker 45*5b0c9b98SJohan Jonker clocks: 46*5b0c9b98SJohan Jonker maxItems: 1 47*5b0c9b98SJohan Jonker 48*5b0c9b98SJohan Jonker clock-names: 49*5b0c9b98SJohan Jonker const: xin24m 50*5b0c9b98SJohan Jonker 51*5b0c9b98SJohan Jonker rockchip,grf: 52*5b0c9b98SJohan Jonker $ref: /schemas/types.yaml#/definitions/phandle 53*5b0c9b98SJohan Jonker description: 54*5b0c9b98SJohan Jonker Phandle to the syscon managing the "general register files" (GRF), 55*5b0c9b98SJohan Jonker if missing pll rates are not changeable, due to the missing pll 56*5b0c9b98SJohan Jonker lock status. 57*5b0c9b98SJohan Jonker 58*5b0c9b98SJohan Jonkerrequired: 59*5b0c9b98SJohan Jonker - compatible 60*5b0c9b98SJohan Jonker - reg 61*5b0c9b98SJohan Jonker - "#clock-cells" 62*5b0c9b98SJohan Jonker - "#reset-cells" 63*5b0c9b98SJohan Jonker 64*5b0c9b98SJohan JonkeradditionalProperties: false 65*5b0c9b98SJohan Jonker 66*5b0c9b98SJohan Jonkerexamples: 67*5b0c9b98SJohan Jonker - | 68*5b0c9b98SJohan Jonker cru: clock-controller@20000000 { 69*5b0c9b98SJohan Jonker compatible = "rockchip,rk3228-cru"; 70*5b0c9b98SJohan Jonker reg = <0x20000000 0x1000>; 71*5b0c9b98SJohan Jonker rockchip,grf = <&grf>; 72*5b0c9b98SJohan Jonker #clock-cells = <1>; 73*5b0c9b98SJohan Jonker #reset-cells = <1>; 74*5b0c9b98SJohan Jonker }; 75