1*54e184f0SAnup Patel# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*54e184f0SAnup Patel%YAML 1.2 3*54e184f0SAnup Patel--- 4*54e184f0SAnup Patel$id: http://devicetree.org/schemas/clock/riscv,rpmi-mpxy-clock.yaml# 5*54e184f0SAnup Patel$schema: http://devicetree.org/meta-schemas/core.yaml# 6*54e184f0SAnup Patel 7*54e184f0SAnup Pateltitle: RISC-V RPMI clock service group based message proxy 8*54e184f0SAnup Patel 9*54e184f0SAnup Patelmaintainers: 10*54e184f0SAnup Patel - Anup Patel <anup@brainfault.org> 11*54e184f0SAnup Patel 12*54e184f0SAnup Pateldescription: | 13*54e184f0SAnup Patel The RISC-V Platform Management Interface (RPMI) [1] defines a 14*54e184f0SAnup Patel messaging protocol which is modular and extensible. The supervisor 15*54e184f0SAnup Patel software can send/receive RPMI messages via SBI MPXY extension [2] 16*54e184f0SAnup Patel or some dedicated supervisor-mode RPMI transport. 17*54e184f0SAnup Patel 18*54e184f0SAnup Patel The RPMI specification [1] defines clock service group for accessing 19*54e184f0SAnup Patel system clocks managed by a platform microcontroller. The SBI implementation 20*54e184f0SAnup Patel (machine mode firmware or hypervisor) can implement an SBI MPXY channel 21*54e184f0SAnup Patel to allow RPMI clock service group access to the supervisor software. 22*54e184f0SAnup Patel 23*54e184f0SAnup Patel =========================================== 24*54e184f0SAnup Patel References 25*54e184f0SAnup Patel =========================================== 26*54e184f0SAnup Patel 27*54e184f0SAnup Patel [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) 28*54e184f0SAnup Patel https://github.com/riscv-non-isa/riscv-rpmi/releases 29*54e184f0SAnup Patel 30*54e184f0SAnup Patel [2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) 31*54e184f0SAnup Patel https://github.com/riscv-non-isa/riscv-sbi-doc/releases 32*54e184f0SAnup Patel 33*54e184f0SAnup Patelproperties: 34*54e184f0SAnup Patel compatible: 35*54e184f0SAnup Patel description: 36*54e184f0SAnup Patel Intended for use by the SBI implementation. 37*54e184f0SAnup Patel const: riscv,rpmi-mpxy-clock 38*54e184f0SAnup Patel 39*54e184f0SAnup Patel mboxes: 40*54e184f0SAnup Patel maxItems: 1 41*54e184f0SAnup Patel description: 42*54e184f0SAnup Patel Mailbox channel of the underlying RPMI transport. 43*54e184f0SAnup Patel 44*54e184f0SAnup Patel riscv,sbi-mpxy-channel-id: 45*54e184f0SAnup Patel $ref: /schemas/types.yaml#/definitions/uint32 46*54e184f0SAnup Patel description: 47*54e184f0SAnup Patel The SBI MPXY channel id to be used for providing RPMI access to 48*54e184f0SAnup Patel the supervisor software. 49*54e184f0SAnup Patel 50*54e184f0SAnup Patelrequired: 51*54e184f0SAnup Patel - compatible 52*54e184f0SAnup Patel - mboxes 53*54e184f0SAnup Patel - riscv,sbi-mpxy-channel-id 54*54e184f0SAnup Patel 55*54e184f0SAnup PateladditionalProperties: false 56*54e184f0SAnup Patel 57*54e184f0SAnup Patelexamples: 58*54e184f0SAnup Patel - | 59*54e184f0SAnup Patel clock-service { 60*54e184f0SAnup Patel compatible = "riscv,rpmi-mpxy-clock"; 61*54e184f0SAnup Patel mboxes = <&rpmi_shmem_mbox 0x8>; 62*54e184f0SAnup Patel riscv,sbi-mpxy-channel-id = <0x1000>; 63*54e184f0SAnup Patel }; 64*54e184f0SAnup Patel... 65