1*b3858302SAnup Patel# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*b3858302SAnup Patel%YAML 1.2 3*b3858302SAnup Patel--- 4*b3858302SAnup Patel$id: http://devicetree.org/schemas/clock/riscv,rpmi-clock.yaml# 5*b3858302SAnup Patel$schema: http://devicetree.org/meta-schemas/core.yaml# 6*b3858302SAnup Patel 7*b3858302SAnup Pateltitle: RISC-V RPMI clock service group based clock controller 8*b3858302SAnup Patel 9*b3858302SAnup Patelmaintainers: 10*b3858302SAnup Patel - Anup Patel <anup@brainfault.org> 11*b3858302SAnup Patel 12*b3858302SAnup Pateldescription: | 13*b3858302SAnup Patel The RISC-V Platform Management Interface (RPMI) [1] defines a 14*b3858302SAnup Patel messaging protocol which is modular and extensible. The supervisor 15*b3858302SAnup Patel software can send/receive RPMI messages via SBI MPXY extension [2] 16*b3858302SAnup Patel or some dedicated supervisor-mode RPMI transport. 17*b3858302SAnup Patel 18*b3858302SAnup Patel The RPMI specification [1] defines clock service group for accessing 19*b3858302SAnup Patel system clocks managed by a platform microcontroller. The supervisor 20*b3858302SAnup Patel software can access RPMI clock service group via SBI MPXY channel or 21*b3858302SAnup Patel some dedicated supervisor-mode RPMI transport. 22*b3858302SAnup Patel 23*b3858302SAnup Patel =========================================== 24*b3858302SAnup Patel References 25*b3858302SAnup Patel =========================================== 26*b3858302SAnup Patel 27*b3858302SAnup Patel [1] RISC-V Platform Management Interface (RPMI) v1.0 (or higher) 28*b3858302SAnup Patel https://github.com/riscv-non-isa/riscv-rpmi/releases 29*b3858302SAnup Patel 30*b3858302SAnup Patel [2] RISC-V Supervisor Binary Interface (SBI) v3.0 (or higher) 31*b3858302SAnup Patel https://github.com/riscv-non-isa/riscv-sbi-doc/releases 32*b3858302SAnup Patel 33*b3858302SAnup Patelproperties: 34*b3858302SAnup Patel compatible: 35*b3858302SAnup Patel description: 36*b3858302SAnup Patel Intended for use by the supervisor software. 37*b3858302SAnup Patel const: riscv,rpmi-clock 38*b3858302SAnup Patel 39*b3858302SAnup Patel mboxes: 40*b3858302SAnup Patel maxItems: 1 41*b3858302SAnup Patel description: 42*b3858302SAnup Patel Mailbox channel of the underlying RPMI transport or SBI message proxy channel. 43*b3858302SAnup Patel 44*b3858302SAnup Patel "#clock-cells": 45*b3858302SAnup Patel const: 1 46*b3858302SAnup Patel description: 47*b3858302SAnup Patel Platform specific CLOCK_ID as defined by the RISC-V Platform Management 48*b3858302SAnup Patel Interface (RPMI) specification. 49*b3858302SAnup Patel 50*b3858302SAnup Patelrequired: 51*b3858302SAnup Patel - compatible 52*b3858302SAnup Patel - mboxes 53*b3858302SAnup Patel - "#clock-cells" 54*b3858302SAnup Patel 55*b3858302SAnup PateladditionalProperties: false 56*b3858302SAnup Patel 57*b3858302SAnup Patelexamples: 58*b3858302SAnup Patel - | 59*b3858302SAnup Patel clock-controller { 60*b3858302SAnup Patel compatible = "riscv,rpmi-clock"; 61*b3858302SAnup Patel mboxes = <&mpxy_mbox 0x1000 0x0>; 62*b3858302SAnup Patel #clock-cells = <1>; 63*b3858302SAnup Patel }; 64*b3858302SAnup Patel... 65