xref: /linux/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
8
9maintainers:
10  - Geert Uytterhoeven <geert+renesas@glider.be>
11
12description: |
13  On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
14  Standby Mode share the same register block. On RZ/V2M, the functionality is
15  similar, but does not have Clock Monitor Registers.
16
17  They provide the following functionalities:
18    - The CPG block generates various core clocks,
19    - The Module Standby Mode block provides two functions:
20        1. Module Standby, providing a Clock Domain to control the clock supply
21           to individual SoC devices,
22        2. Reset Control, to perform a software reset of individual SoC devices.
23
24properties:
25  compatible:
26    enum:
27      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
28      - renesas,r9a07g044-cpg # RZ/G2{L,LC}
29      - renesas,r9a07g054-cpg # RZ/V2L
30      - renesas,r9a08g045-cpg # RZ/G3S
31      - renesas,r9a09g011-cpg # RZ/V2M
32
33  reg:
34    maxItems: 1
35
36  clocks:
37    maxItems: 1
38
39  clock-names:
40    description:
41      Clock source to CPG can be either from external clock input (EXCLK) or
42      crystal oscillator (XIN/XOUT).
43    const: extal
44
45  '#clock-cells':
46    description: |
47      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
48        and a core clock reference, as defined in
49        <dt-bindings/clock/r9a0*-cpg.h>,
50      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
51        a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.
52    const: 2
53
54  '#power-domain-cells':
55    description:
56      SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
57      can be power-managed through Module Standby should refer to the CPG device
58      node in their "power-domains" property, as documented by the generic PM
59      Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
60      The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could
61      be used to reference individual CPG power domains.
62
63  '#reset-cells':
64    description:
65      The single reset specifier cell must be the reset number, as defined in
66      <dt-bindings/clock/r9a0*-cpg.h>.
67    const: 1
68
69required:
70  - compatible
71  - reg
72  - clocks
73  - clock-names
74  - '#clock-cells'
75  - '#power-domain-cells'
76  - '#reset-cells'
77
78additionalProperties: false
79
80allOf:
81  - if:
82      properties:
83        compatible:
84          contains:
85            const: renesas,r9a08g045-cpg
86    then:
87      properties:
88        '#power-domain-cells':
89          const: 1
90    else:
91      properties:
92        '#power-domain-cells':
93          const: 0
94
95examples:
96  - |
97    cpg: clock-controller@11010000 {
98            compatible = "renesas,r9a07g044-cpg";
99            reg = <0x11010000 0x10000>;
100            clocks = <&extal_clk>;
101            clock-names = "extal";
102            #clock-cells = <2>;
103            #power-domain-cells = <0>;
104            #reset-cells = <1>;
105    };
106