xref: /linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml (revision beaea9c4ba2d8ef1b10223dc3a75a7d7be3e5cd9) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas Clock Pulse Generator / Module Standby and Software Reset
8
9maintainers:
10  - Geert Uytterhoeven <geert+renesas@glider.be>
11
12description: |
13  On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
14  and MSSR (Module Standby and Software Reset) blocks are intimately connected,
15  and share the same register block.
16
17  They provide the following functionalities:
18    - The CPG block generates various core clocks,
19    - The MSSR block provides two functions:
20        1. Module Standby, providing a Clock Domain to control the clock supply
21           to individual SoC devices,
22        2. Reset Control, to perform a software reset of individual SoC devices.
23
24properties:
25  compatible:
26    enum:
27      - renesas,r7s9210-cpg-mssr  # RZ/A2
28      - renesas,r8a7742-cpg-mssr  # RZ/G1H
29      - renesas,r8a7743-cpg-mssr  # RZ/G1M
30      - renesas,r8a7744-cpg-mssr  # RZ/G1N
31      - renesas,r8a7745-cpg-mssr  # RZ/G1E
32      - renesas,r8a77470-cpg-mssr # RZ/G1C
33      - renesas,r8a774a1-cpg-mssr # RZ/G2M
34      - renesas,r8a774a3-cpg-mssr # RZ/G2M v3.0
35      - renesas,r8a774b1-cpg-mssr # RZ/G2N
36      - renesas,r8a774c0-cpg-mssr # RZ/G2E
37      - renesas,r8a774e1-cpg-mssr # RZ/G2H
38      - renesas,r8a7790-cpg-mssr  # R-Car H2
39      - renesas,r8a7791-cpg-mssr  # R-Car M2-W
40      - renesas,r8a7792-cpg-mssr  # R-Car V2H
41      - renesas,r8a7793-cpg-mssr  # R-Car M2-N
42      - renesas,r8a7794-cpg-mssr  # R-Car E2
43      - renesas,r8a7795-cpg-mssr  # R-Car H3
44      - renesas,r8a7796-cpg-mssr  # R-Car M3-W
45      - renesas,r8a77961-cpg-mssr # R-Car M3-W+
46      - renesas,r8a77965-cpg-mssr # R-Car M3-N
47      - renesas,r8a77970-cpg-mssr # R-Car V3M
48      - renesas,r8a77980-cpg-mssr # R-Car V3H
49      - renesas,r8a77990-cpg-mssr # R-Car E3
50      - renesas,r8a77995-cpg-mssr # R-Car D3
51      - renesas,r8a779a0-cpg-mssr # R-Car V3U
52      - renesas,r8a779f0-cpg-mssr # R-Car S4-8
53      - renesas,r8a779g0-cpg-mssr # R-Car V4H
54      - renesas,r8a779h0-cpg-mssr # R-Car V4M
55      - renesas,r9a09g077-cpg-mssr # RZ/T2H
56      - renesas,r9a09g087-cpg-mssr # RZ/N2H
57
58  reg:
59    minItems: 1
60    items:
61      - description: base address of register block 0
62      - description: base address of register block 1
63    description: base addresses of clock controller. Some controllers
64      (like r9a09g077) use two blocks instead of a single one.
65
66  clocks:
67    minItems: 1
68    maxItems: 2
69
70  clock-names:
71    minItems: 1
72    maxItems: 2
73    items:
74      enum:
75        - extal     # All
76        - extalr    # Most R-Car Gen3 and RZ/G2
77        - usb_extal # Most R-Car Gen2 and RZ/G1
78
79  '#clock-cells':
80    description: |
81      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
82        and a core clock reference, as defined in
83        <dt-bindings/clock/*-cpg-mssr.h>
84      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
85        a module number, as defined in the datasheet.
86    const: 2
87
88  '#power-domain-cells':
89    description:
90      SoC devices that are part of the CPG/MSSR Clock Domain and can be
91      power-managed through Module Standby should refer to the CPG device node
92      in their "power-domains" property, as documented by the generic PM Domain
93      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
94    const: 0
95
96  '#reset-cells':
97    description:
98      The single reset specifier cell must be the module number, as defined in
99      the datasheet.
100    const: 1
101
102
103required:
104  - compatible
105  - reg
106  - clocks
107  - clock-names
108  - '#clock-cells'
109  - '#power-domain-cells'
110
111allOf:
112  - if:
113      properties:
114        compatible:
115          contains:
116            enum:
117              - renesas,r9a09g077-cpg-mssr
118              - renesas,r9a09g087-cpg-mssr
119    then:
120      properties:
121        reg:
122          minItems: 2
123        clock-names:
124          items:
125            - const: extal
126    else:
127      properties:
128        reg:
129          maxItems: 1
130  - if:
131      not:
132        properties:
133          compatible:
134            items:
135              enum:
136                - renesas,r7s9210-cpg-mssr
137    then:
138      required:
139        - '#reset-cells'
140
141additionalProperties: false
142
143examples:
144  - |
145    cpg: clock-controller@e6150000 {
146            compatible = "renesas,r8a7795-cpg-mssr";
147            reg = <0xe6150000 0x1000>;
148            clocks = <&extal_clk>, <&extalr_clk>;
149            clock-names = "extal", "extalr";
150            #clock-cells = <2>;
151            #power-domain-cells = <0>;
152            #reset-cells = <1>;
153    };
154