xref: /linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml (revision 8e1bb4a41aa78d6105e59186af3dcd545fc66e70) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas Clock Pulse Generator / Module Standby and Software Reset
8
9maintainers:
10  - Geert Uytterhoeven <geert+renesas@glider.be>
11
12description: |
13  On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
14  and MSSR (Module Standby and Software Reset) blocks are intimately connected,
15  and share the same register block.
16
17  They provide the following functionalities:
18    - The CPG block generates various core clocks,
19    - The MSSR block provides two functions:
20        1. Module Standby, providing a Clock Domain to control the clock supply
21           to individual SoC devices,
22        2. Reset Control, to perform a software reset of individual SoC devices.
23
24properties:
25  compatible:
26    enum:
27      - renesas,r7s9210-cpg-mssr  # RZ/A2
28      - renesas,r8a7742-cpg-mssr  # RZ/G1H
29      - renesas,r8a7743-cpg-mssr  # RZ/G1M
30      - renesas,r8a7744-cpg-mssr  # RZ/G1N
31      - renesas,r8a7745-cpg-mssr  # RZ/G1E
32      - renesas,r8a77470-cpg-mssr # RZ/G1C
33      - renesas,r8a774a1-cpg-mssr # RZ/G2M
34      - renesas,r8a774b1-cpg-mssr # RZ/G2N
35      - renesas,r8a774c0-cpg-mssr # RZ/G2E
36      - renesas,r8a774e1-cpg-mssr # RZ/G2H
37      - renesas,r8a7790-cpg-mssr  # R-Car H2
38      - renesas,r8a7791-cpg-mssr  # R-Car M2-W
39      - renesas,r8a7792-cpg-mssr  # R-Car V2H
40      - renesas,r8a7793-cpg-mssr  # R-Car M2-N
41      - renesas,r8a7794-cpg-mssr  # R-Car E2
42      - renesas,r8a7795-cpg-mssr  # R-Car H3
43      - renesas,r8a7796-cpg-mssr  # R-Car M3-W
44      - renesas,r8a77961-cpg-mssr # R-Car M3-W+
45      - renesas,r8a77965-cpg-mssr # R-Car M3-N
46      - renesas,r8a77970-cpg-mssr # R-Car V3M
47      - renesas,r8a77980-cpg-mssr # R-Car V3H
48      - renesas,r8a77990-cpg-mssr # R-Car E3
49      - renesas,r8a77995-cpg-mssr # R-Car D3
50      - renesas,r8a779a0-cpg-mssr # R-Car V3U
51      - renesas,r8a779f0-cpg-mssr # R-Car S4-8
52      - renesas,r8a779g0-cpg-mssr # R-Car V4H
53      - renesas,r8a779h0-cpg-mssr # R-Car V4M
54
55  reg:
56    maxItems: 1
57
58  clocks:
59    minItems: 1
60    maxItems: 2
61
62  clock-names:
63    minItems: 1
64    maxItems: 2
65    items:
66      enum:
67        - extal     # All
68        - extalr    # Most R-Car Gen3 and RZ/G2
69        - usb_extal # Most R-Car Gen2 and RZ/G1
70
71  '#clock-cells':
72    description: |
73      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
74        and a core clock reference, as defined in
75        <dt-bindings/clock/*-cpg-mssr.h>
76      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
77        a module number, as defined in the datasheet.
78    const: 2
79
80  '#power-domain-cells':
81    description:
82      SoC devices that are part of the CPG/MSSR Clock Domain and can be
83      power-managed through Module Standby should refer to the CPG device node
84      in their "power-domains" property, as documented by the generic PM Domain
85      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
86    const: 0
87
88  '#reset-cells':
89    description:
90      The single reset specifier cell must be the module number, as defined in
91      the datasheet.
92    const: 1
93
94if:
95  not:
96    properties:
97      compatible:
98        items:
99          enum:
100            - renesas,r7s9210-cpg-mssr
101then:
102  required:
103    - '#reset-cells'
104
105required:
106  - compatible
107  - reg
108  - clocks
109  - clock-names
110  - '#clock-cells'
111  - '#power-domain-cells'
112
113additionalProperties: false
114
115examples:
116  - |
117    cpg: clock-controller@e6150000 {
118            compatible = "renesas,r8a7795-cpg-mssr";
119            reg = <0xe6150000 0x1000>;
120            clocks = <&extal_clk>, <&extalr_clk>;
121            clock-names = "extal", "extalr";
122            #clock-cells = <2>;
123            #power-domain-cells = <0>;
124            #reset-cells = <1>;
125    };
126