xref: /linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml (revision 26fbb4c8c7c3ee9a4c3b4de555a8587b5a19154e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Renesas Clock Pulse Generator / Module Standby and Software Reset
8
9maintainers:
10  - Geert Uytterhoeven <geert+renesas@glider.be>
11
12description: |
13  On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
14  and MSSR (Module Standby and Software Reset) blocks are intimately connected,
15  and share the same register block.
16
17  They provide the following functionalities:
18    - The CPG block generates various core clocks,
19    - The MSSR block provides two functions:
20        1. Module Standby, providing a Clock Domain to control the clock supply
21           to individual SoC devices,
22        2. Reset Control, to perform a software reset of individual SoC devices.
23
24properties:
25  compatible:
26    enum:
27      - renesas,r7s9210-cpg-mssr  # RZ/A2
28      - renesas,r8a7742-cpg-mssr  # RZ/G1H
29      - renesas,r8a7743-cpg-mssr  # RZ/G1M
30      - renesas,r8a7744-cpg-mssr  # RZ/G1N
31      - renesas,r8a7745-cpg-mssr  # RZ/G1E
32      - renesas,r8a77470-cpg-mssr # RZ/G1C
33      - renesas,r8a774a1-cpg-mssr # RZ/G2M
34      - renesas,r8a774b1-cpg-mssr # RZ/G2N
35      - renesas,r8a774c0-cpg-mssr # RZ/G2E
36      - renesas,r8a774e1-cpg-mssr # RZ/G2H
37      - renesas,r8a7790-cpg-mssr  # R-Car H2
38      - renesas,r8a7791-cpg-mssr  # R-Car M2-W
39      - renesas,r8a7792-cpg-mssr  # R-Car V2H
40      - renesas,r8a7793-cpg-mssr  # R-Car M2-N
41      - renesas,r8a7794-cpg-mssr  # R-Car E2
42      - renesas,r8a7795-cpg-mssr  # R-Car H3
43      - renesas,r8a7796-cpg-mssr  # R-Car M3-W
44      - renesas,r8a77961-cpg-mssr # R-Car M3-W+
45      - renesas,r8a77965-cpg-mssr # R-Car M3-N
46      - renesas,r8a77970-cpg-mssr # R-Car V3M
47      - renesas,r8a77980-cpg-mssr # R-Car V3H
48      - renesas,r8a77990-cpg-mssr # R-Car E3
49      - renesas,r8a77995-cpg-mssr # R-Car D3
50      - renesas,r8a779a0-cpg-mssr # R-Car V3U
51
52  reg:
53    maxItems: 1
54
55  clocks:
56    minItems: 1
57    maxItems: 2
58
59  clock-names:
60    minItems: 1
61    maxItems: 2
62    items:
63      enum:
64        - extal     # All
65        - extalr    # Most R-Car Gen3 and RZ/G2
66        - usb_extal # Most R-Car Gen2 and RZ/G1
67
68  '#clock-cells':
69    description: |
70      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
71        and a core clock reference, as defined in
72        <dt-bindings/clock/*-cpg-mssr.h>
73      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
74        a module number, as defined in the datasheet.
75    const: 2
76
77  '#power-domain-cells':
78    description:
79      SoC devices that are part of the CPG/MSSR Clock Domain and can be
80      power-managed through Module Standby should refer to the CPG device node
81      in their "power-domains" property, as documented by the generic PM Domain
82      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
83    const: 0
84
85  '#reset-cells':
86    description:
87      The single reset specifier cell must be the module number, as defined in
88      the datasheet.
89    const: 1
90
91if:
92  not:
93    properties:
94      compatible:
95        items:
96          enum:
97            - renesas,r7s9210-cpg-mssr
98then:
99  required:
100    - '#reset-cells'
101
102required:
103  - compatible
104  - reg
105  - clocks
106  - clock-names
107  - '#clock-cells'
108  - '#power-domain-cells'
109
110additionalProperties: false
111
112examples:
113  - |
114    cpg: clock-controller@e6150000 {
115            compatible = "renesas,r8a7795-cpg-mssr";
116            reg = <0xe6150000 0x1000>;
117            clocks = <&extal_clk>, <&extalr_clk>;
118            clock-names = "extal", "extalr";
119            #clock-cells = <2>;
120            #power-domain-cells = <0>;
121            #reset-cells = <1>;
122    };
123