1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas Clock Pulse Generator (CPG) 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 12description: 13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It 14 includes PLLs, and fixed and variable ratio dividers. 15 16 The CPG may also provide a Clock Domain for SoC devices, in combination with 17 the CPG Module Stop (MSTP) Clocks. 18 19properties: 20 compatible: 21 oneOf: 22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6 23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1 24 - const: renesas,r8a7778-cpg-clocks # R-Car M1 25 - const: renesas,r8a7779-cpg-clocks # R-Car H1 26 - items: 27 - enum: 28 - renesas,r7s72100-cpg-clocks # RZ/A1H 29 - const: renesas,rz-cpg-clocks # RZ/A1 30 - const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5 31 32 reg: 33 maxItems: 1 34 35 clocks: 36 minItems: 1 37 maxItems: 3 38 39 '#clock-cells': 40 const: 1 41 42 clock-output-names: 43 minItems: 3 44 maxItems: 19 45 46 renesas,mode: 47 description: Board-specific settings of the MD_CK* bits on R-Mobile A1 48 $ref: /schemas/types.yaml#/definitions/uint32 49 minimum: 0 50 maximum: 7 51 52 '#power-domain-cells': 53 const: 0 54 55required: 56 - compatible 57 - reg 58 - clocks 59 - '#clock-cells' 60 - clock-output-names 61 62allOf: 63 - if: 64 properties: 65 compatible: 66 contains: 67 const: renesas,r8a73a4-cpg-clocks 68 then: 69 properties: 70 clocks: 71 items: 72 - description: extal1 73 - description: extal2 74 75 clock-output-names: 76 items: 77 - const: main 78 - const: pll0 79 - const: pll1 80 - const: pll2 81 - const: pll2s 82 - const: pll2h 83 - const: z 84 - const: z2 85 - const: i 86 - const: m3 87 - const: b 88 - const: m1 89 - const: m2 90 - const: zx 91 - const: zs 92 - const: hp 93 - const: ztr 94 - const: zt 95 96 - if: 97 properties: 98 compatible: 99 contains: 100 const: renesas,r8a7740-cpg-clocks 101 then: 102 properties: 103 clocks: 104 items: 105 - description: extal1 106 - description: extal2 107 - description: extalr 108 109 clock-output-names: 110 items: 111 - const: system 112 - const: pllc0 113 - const: pllc1 114 - const: pllc2 115 - const: r 116 - const: usb24s 117 - const: i 118 - const: zg 119 - const: b 120 - const: m1 121 - const: hp 122 - const: hpp 123 - const: usbp 124 - const: s 125 - const: zb 126 - const: m3 127 - const: cp 128 - const: ztr 129 - const: zt 130 131 required: 132 - renesas,mode 133 134 - if: 135 properties: 136 compatible: 137 contains: 138 const: renesas,r8a7778-cpg-clocks 139 then: 140 properties: 141 clocks: 142 maxItems: 1 143 144 clock-output-names: 145 items: 146 - const: plla 147 - const: pllb 148 - const: b 149 - const: out 150 - const: p 151 - const: s 152 - const: s1 153 154 - if: 155 properties: 156 compatible: 157 contains: 158 const: renesas,r8a7779-cpg-clocks 159 then: 160 properties: 161 clocks: 162 maxItems: 1 163 164 clock-output-names: 165 items: 166 - const: plla 167 - const: z 168 - const: zs 169 - const: s 170 - const: s1 171 - const: p 172 - const: b 173 - const: out 174 175 - if: 176 properties: 177 compatible: 178 contains: 179 const: renesas,r7s72100-cpg-clocks 180 then: 181 properties: 182 clocks: 183 items: 184 - description: extal1 185 - description: usb_x1 186 187 clock-output-names: 188 items: 189 - const: pll 190 - const: i 191 - const: g 192 193 - if: 194 properties: 195 compatible: 196 contains: 197 const: renesas,sh73a0-cpg-clocks 198 then: 199 properties: 200 clocks: 201 items: 202 - description: extal1 203 - description: extal2 204 205 clock-output-names: 206 items: 207 - const: main 208 - const: pll0 209 - const: pll1 210 - const: pll2 211 - const: pll3 212 - const: dsi0phy 213 - const: dsi1phy 214 - const: zg 215 - const: m3 216 - const: b 217 - const: m1 218 - const: m2 219 - const: z 220 - const: zx 221 - const: hp 222 223 - if: 224 properties: 225 compatible: 226 contains: 227 enum: 228 - renesas,r8a7778-cpg-clocks 229 - renesas,r8a7779-cpg-clocks 230 - renesas,rz-cpg-clocks 231 then: 232 required: 233 - '#power-domain-cells' 234 235additionalProperties: false 236 237examples: 238 - | 239 #include <dt-bindings/clock/r8a7740-clock.h> 240 cpg_clocks: cpg_clocks@e6150000 { 241 compatible = "renesas,r8a7740-cpg-clocks"; 242 reg = <0xe6150000 0x10000>; 243 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>; 244 #clock-cells = <1>; 245 clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r", 246 "usb24s", "i", "zg", "b", "m1", "hp", "hpp", 247 "usbp", "s", "zb", "m3", "cp", "ztr", "zt"; 248 renesas,mode = <0x05>; 249 }; 250