xref: /linux/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml (revision b501d4dc83aa3940189b68045cadc8b3eac73988) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/renesas,versaclock7.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas Versaclock7 Programmable Clock
8
9maintainers:
10  - Alex Helms <alexander.helms.jy@renesas.com>
11
12description: |
13  Renesas Versaclock7 is a family of configurable clock generator and
14  jitter attenuator ICs with fractional and integer dividers.
15
16properties:
17  '#clock-cells':
18    const: 1
19
20  compatible:
21    enum:
22      - renesas,rc21008a
23
24  reg:
25    maxItems: 1
26
27  clocks:
28    items:
29      - description: External crystal or oscillator
30
31  clock-names:
32    items:
33      - const: xin
34
35required:
36  - '#clock-cells'
37  - compatible
38  - reg
39  - clocks
40  - clock-names
41
42additionalProperties: false
43
44examples:
45  - |
46    vc7_xin: clock {
47        compatible = "fixed-clock";
48        #clock-cells = <0>;
49        clock-frequency = <49152000>;
50    };
51
52    i2c@0 {
53        reg = <0x0 0x100>;
54        #address-cells = <1>;
55        #size-cells = <0>;
56
57        vc7: clock-controller@9 {
58            compatible = "renesas,rc21008a";
59            reg = <0x9>;
60            #clock-cells = <1>;
61            clocks = <&vc7_xin>;
62            clock-names = "xin";
63        };
64    };
65