xref: /linux/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml (revision 502d45774af09f1c681c754c4b7cdfb5d7f72fd9)
1*88656a46SGeert Uytterhoeven# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*88656a46SGeert Uytterhoeven%YAML 1.2
3*88656a46SGeert Uytterhoeven---
4*88656a46SGeert Uytterhoeven$id: http://devicetree.org/schemas/clock/renesas,r8a78000-cpg.yaml#
5*88656a46SGeert Uytterhoeven$schema: http://devicetree.org/meta-schemas/core.yaml#
6*88656a46SGeert Uytterhoeven
7*88656a46SGeert Uytterhoeventitle: Renesas R-Car X5H Clock Pulse Generator
8*88656a46SGeert Uytterhoeven
9*88656a46SGeert Uytterhoevenmaintainers:
10*88656a46SGeert Uytterhoeven  - Geert Uytterhoeven <geert+renesas@glider.be>
11*88656a46SGeert Uytterhoeven
12*88656a46SGeert Uytterhoevendescription:
13*88656a46SGeert Uytterhoeven  The R-Car X5H Clock Pulse Generator (CLK CONTROL) consists of oscillators,
14*88656a46SGeert Uytterhoeven  PLL circuits, clock dividers and clock control circuits.  It provides various
15*88656a46SGeert Uytterhoeven  clocks for other modules.
16*88656a46SGeert Uytterhoeven
17*88656a46SGeert Uytterhoevenproperties:
18*88656a46SGeert Uytterhoeven  compatible:
19*88656a46SGeert Uytterhoeven    const: renesas,r8a78000-cpg
20*88656a46SGeert Uytterhoeven
21*88656a46SGeert Uytterhoeven  reg:
22*88656a46SGeert Uytterhoeven    maxItems: 1
23*88656a46SGeert Uytterhoeven
24*88656a46SGeert Uytterhoeven  clocks:
25*88656a46SGeert Uytterhoeven    maxItems: 2
26*88656a46SGeert Uytterhoeven
27*88656a46SGeert Uytterhoeven  clock-names:
28*88656a46SGeert Uytterhoeven    items:
29*88656a46SGeert Uytterhoeven      - const: extal
30*88656a46SGeert Uytterhoeven      - const: extalr
31*88656a46SGeert Uytterhoeven
32*88656a46SGeert Uytterhoeven  '#clock-cells':
33*88656a46SGeert Uytterhoeven    description:
34*88656a46SGeert Uytterhoeven      The single clock specifier cell must be the clock number, as defined in
35*88656a46SGeert Uytterhoeven      <dt-bindings/clock/renesas,r8a78000-cpg.h>.
36*88656a46SGeert Uytterhoeven    const: 1
37*88656a46SGeert Uytterhoeven
38*88656a46SGeert Uytterhoevenrequired:
39*88656a46SGeert Uytterhoeven  - compatible
40*88656a46SGeert Uytterhoeven  - reg
41*88656a46SGeert Uytterhoeven  - clocks
42*88656a46SGeert Uytterhoeven  - clock-names
43*88656a46SGeert Uytterhoeven  - '#clock-cells'
44*88656a46SGeert Uytterhoeven
45*88656a46SGeert UytterhoevenadditionalProperties: false
46*88656a46SGeert Uytterhoeven
47*88656a46SGeert Uytterhoevenexamples:
48*88656a46SGeert Uytterhoeven  - |
49*88656a46SGeert Uytterhoeven    clock-controller@c1320000 {
50*88656a46SGeert Uytterhoeven            compatible = "renesas,r8a78000-cpg";
51*88656a46SGeert Uytterhoeven            reg = <0xc1320000 0x10000>;
52*88656a46SGeert Uytterhoeven            clocks = <&extal_clk>, <&extalr_clk>;
53*88656a46SGeert Uytterhoeven            clock-names = "extal", "extalr";
54*88656a46SGeert Uytterhoeven            #clock-cells = <1>;
55*88656a46SGeert Uytterhoeven    };
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