xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml (revision d30c1683aaecb93d2ab95685dc4300a33d3cea7a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8750-gcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on SM8750
8
9maintainers:
10  - Taniya Das <quic_tdas@quicinc.com>
11
12description: |
13  Qualcomm global clock control module provides the clocks, resets and power
14  domains on SM8750
15
16  See also:
17    include/dt-bindings/clock/qcom,kaanapali-gcc.h
18    include/dt-bindings/clock/qcom,sm8750-gcc.h
19
20properties:
21  compatible:
22    enum:
23      - qcom,kaanapali-gcc
24      - qcom,sm8750-gcc
25
26  clocks:
27    items:
28      - description: Board XO source
29      - description: Board Always On XO source
30      - description: Sleep clock source
31      - description: PCIE 0 Pipe clock source
32      - description: UFS Phy Rx symbol 0 clock source
33      - description: UFS Phy Rx symbol 1 clock source
34      - description: UFS Phy Tx symbol 0 clock source
35      - description: USB3 Phy wrapper pipe clock source
36
37required:
38  - compatible
39  - clocks
40  - '#power-domain-cells'
41
42allOf:
43  - $ref: qcom,gcc.yaml#
44
45unevaluatedProperties: false
46
47examples:
48  - |
49    #include <dt-bindings/clock/qcom,rpmh.h>
50    clock-controller@100000 {
51      compatible = "qcom,sm8750-gcc";
52      reg = <0x00100000 0x001f4200>;
53      clocks = <&rpmhcc RPMH_CXO_CLK>,
54               <&rpmhcc RPMH_CXO_CLK_A>,
55               <&sleep_clk>,
56               <&pcie0_phy>,
57               <&ufs_mem_phy 0>,
58               <&ufs_mem_phy 1>,
59               <&ufs_mem_phy 2>,
60               <&usb_1_qmpphy>;
61      #clock-cells = <1>;
62      #reset-cells = <1>;
63      #power-domain-cells = <1>;
64    };
65
66...
67