xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml (revision eb01fe7abbe2d0b38824d2a93fdb4cc3eaf2ccc1) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock & Reset Controller for SM8550
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Neil Armstrong <neil.armstrong@linaro.org>
12
13description: |
14  Qualcomm display clock control module provides the clocks, resets and power
15  domains on SM8550.
16
17  See also:
18  - include/dt-bindings/clock/qcom,sm8550-dispcc.h
19  - include/dt-bindings/clock/qcom,sm8650-dispcc.h
20  - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
21
22properties:
23  compatible:
24    enum:
25      - qcom,sm8550-dispcc
26      - qcom,sm8650-dispcc
27      - qcom,x1e80100-dispcc
28
29  clocks:
30    items:
31      - description: Board XO source
32      - description: Board Always On XO source
33      - description: Display's AHB clock
34      - description: sleep clock
35      - description: Byte clock from DSI PHY0
36      - description: Pixel clock from DSI PHY0
37      - description: Byte clock from DSI PHY1
38      - description: Pixel clock from DSI PHY1
39      - description: Link clock from DP PHY0
40      - description: VCO DIV clock from DP PHY0
41      - description: Link clock from DP PHY1
42      - description: VCO DIV clock from DP PHY1
43      - description: Link clock from DP PHY2
44      - description: VCO DIV clock from DP PHY2
45      - description: Link clock from DP PHY3
46      - description: VCO DIV clock from DP PHY3
47
48  '#clock-cells':
49    const: 1
50
51  '#reset-cells':
52    const: 1
53
54  '#power-domain-cells':
55    const: 1
56
57  reg:
58    maxItems: 1
59
60  power-domains:
61    description:
62      A phandle and PM domain specifier for the MMCX power domain.
63    maxItems: 1
64
65  required-opps:
66    description:
67      A phandle to an OPP node describing required MMCX performance point.
68    maxItems: 1
69
70required:
71  - compatible
72  - reg
73  - clocks
74  - '#clock-cells'
75  - '#reset-cells'
76  - '#power-domain-cells'
77
78additionalProperties: false
79
80examples:
81  - |
82    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
83    #include <dt-bindings/clock/qcom,rpmh.h>
84    #include <dt-bindings/power/qcom,rpmhpd.h>
85    clock-controller@af00000 {
86      compatible = "qcom,sm8550-dispcc";
87      reg = <0x0af00000 0x10000>;
88      clocks = <&rpmhcc RPMH_CXO_CLK>,
89               <&rpmhcc RPMH_CXO_CLK_A>,
90               <&gcc GCC_DISP_AHB_CLK>,
91               <&sleep_clk>,
92               <&dsi0_phy 0>,
93               <&dsi0_phy 1>,
94               <&dsi1_phy 0>,
95               <&dsi1_phy 1>,
96               <&dp0_phy 0>,
97               <&dp0_phy 1>,
98               <&dp1_phy 0>,
99               <&dp1_phy 1>,
100               <&dp2_phy 0>,
101               <&dp2_phy 1>,
102               <&dp3_phy 0>,
103               <&dp3_phy 1>;
104      #clock-cells = <1>;
105      #reset-cells = <1>;
106      #power-domain-cells = <1>;
107      power-domains = <&rpmhpd RPMHPD_MMCX>;
108      required-opps = <&rpmhpd_opp_low_svs>;
109    };
110...
111