xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock & Reset Controller for SM8550
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Neil Armstrong <neil.armstrong@linaro.org>
12
13description: |
14  Qualcomm display clock control module provides the clocks, resets and power
15  domains on SM8550.
16
17  See also:
18  - include/dt-bindings/clock/qcom,sm8550-dispcc.h
19  - include/dt-bindings/clock/qcom,sm8650-dispcc.h
20  - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
21
22properties:
23  compatible:
24    enum:
25      - qcom,sar2130p-dispcc
26      - qcom,sm8550-dispcc
27      - qcom,sm8650-dispcc
28      - qcom,x1e80100-dispcc
29
30  clocks:
31    items:
32      - description: Board XO source
33      - description: Board Always On XO source
34      - description: Display's AHB clock
35      - description: sleep clock
36      - description: Byte clock from DSI PHY0
37      - description: Pixel clock from DSI PHY0
38      - description: Byte clock from DSI PHY1
39      - description: Pixel clock from DSI PHY1
40      - description: Link clock from DP PHY0
41      - description: VCO DIV clock from DP PHY0
42      - description: Link clock from DP PHY1
43      - description: VCO DIV clock from DP PHY1
44      - description: Link clock from DP PHY2
45      - description: VCO DIV clock from DP PHY2
46      - description: Link clock from DP PHY3
47      - description: VCO DIV clock from DP PHY3
48
49  power-domains:
50    description:
51      A phandle and PM domain specifier for the MMCX power domain.
52    maxItems: 1
53
54  required-opps:
55    description:
56      A phandle to an OPP node describing required MMCX performance point.
57    maxItems: 1
58
59required:
60  - compatible
61  - clocks
62  - '#power-domain-cells'
63
64allOf:
65  - $ref: qcom,gcc.yaml#
66
67unevaluatedProperties: false
68
69examples:
70  - |
71    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
72    #include <dt-bindings/clock/qcom,rpmh.h>
73    #include <dt-bindings/power/qcom,rpmhpd.h>
74    clock-controller@af00000 {
75      compatible = "qcom,sm8550-dispcc";
76      reg = <0x0af00000 0x10000>;
77      clocks = <&rpmhcc RPMH_CXO_CLK>,
78               <&rpmhcc RPMH_CXO_CLK_A>,
79               <&gcc GCC_DISP_AHB_CLK>,
80               <&sleep_clk>,
81               <&dsi0_phy 0>,
82               <&dsi0_phy 1>,
83               <&dsi1_phy 0>,
84               <&dsi1_phy 1>,
85               <&dp0_phy 0>,
86               <&dp0_phy 1>,
87               <&dp1_phy 0>,
88               <&dp1_phy 1>,
89               <&dp2_phy 0>,
90               <&dp2_phy 1>,
91               <&dp3_phy 0>,
92               <&dp3_phy 1>;
93      #clock-cells = <1>;
94      #reset-cells = <1>;
95      #power-domain-cells = <1>;
96      power-domains = <&rpmhpd RPMHPD_MMCX>;
97      required-opps = <&rpmhpd_opp_low_svs>;
98    };
99...
100