xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml (revision d30c1683aaecb93d2ab95685dc4300a33d3cea7a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Video Clock & Reset Controller on SM8450
8
9maintainers:
10  - Taniya Das <taniya.das@oss.qualcomm.com>
11  - Jagadeesh Kona <quic_jkona@quicinc.com>
12
13description: |
14  Qualcomm video clock control module provides the clocks, resets and power
15  domains on SM8450.
16
17  See also:
18    include/dt-bindings/clock/qcom,sm8450-videocc.h
19    include/dt-bindings/clock/qcom,sm8650-videocc.h
20    include/dt-bindings/clock/qcom,sm8750-videocc.h
21
22properties:
23  compatible:
24    enum:
25      - qcom,sm8450-videocc
26      - qcom,sm8475-videocc
27      - qcom,sm8550-videocc
28      - qcom,sm8650-videocc
29      - qcom,sm8750-videocc
30      - qcom,x1e80100-videocc
31
32  clocks:
33    items:
34      - description: Board XO source
35      - description: Video AHB clock from GCC
36
37  power-domains:
38    description:
39      Power domains required for the clock controller to operate
40    items:
41      - description: MMCX power domain
42      - description: MXC power domain
43
44  required-opps:
45    description:
46      OPP nodes that describe required performance points on power domains
47    items:
48      - description: MMCX performance point
49      - description: MXC performance point
50
51required:
52  - compatible
53  - clocks
54  - power-domains
55  - '#power-domain-cells'
56
57allOf:
58  - $ref: qcom,gcc.yaml#
59  - if:
60      properties:
61        compatible:
62          contains:
63            enum:
64              - qcom,sm8450-videocc
65              - qcom,sm8550-videocc
66              - qcom,sm8750-videocc
67    then:
68      required:
69        - required-opps
70
71unevaluatedProperties: false
72
73examples:
74  - |
75    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
76    #include <dt-bindings/clock/qcom,rpmh.h>
77    #include <dt-bindings/power/qcom,rpmhpd.h>
78    videocc: clock-controller@aaf0000 {
79      compatible = "qcom,sm8450-videocc";
80      reg = <0x0aaf0000 0x10000>;
81      clocks = <&rpmhcc RPMH_CXO_CLK>,
82               <&gcc GCC_VIDEO_AHB_CLK>;
83      power-domains = <&rpmhpd RPMHPD_MMCX>,
84                      <&rpmhpd RPMHPD_MXC>;
85      required-opps = <&rpmhpd_opp_low_svs>,
86                      <&rpmhpd_opp_low_svs>;
87      #clock-cells = <1>;
88      #reset-cells = <1>;
89      #power-domain-cells = <1>;
90    };
91...
92