xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Video Clock & Reset Controller on SM8450
8
9maintainers:
10  - Taniya Das <quic_tdas@quicinc.com>
11  - Jagadeesh Kona <quic_jkona@quicinc.com>
12
13description: |
14  Qualcomm video clock control module provides the clocks, resets and power
15  domains on SM8450.
16
17  See also:
18    include/dt-bindings/clock/qcom,sm8450-videocc.h
19    include/dt-bindings/clock/qcom,sm8650-videocc.h
20
21properties:
22  compatible:
23    enum:
24      - qcom,sm8450-videocc
25      - qcom,sm8475-videocc
26      - qcom,sm8550-videocc
27      - qcom,sm8650-videocc
28
29  clocks:
30    items:
31      - description: Board XO source
32      - description: Video AHB clock from GCC
33
34  power-domains:
35    maxItems: 1
36    description:
37      MMCX power domain.
38
39  required-opps:
40    maxItems: 1
41    description:
42      A phandle to an OPP node describing required MMCX performance point.
43
44required:
45  - compatible
46  - clocks
47  - power-domains
48  - '#power-domain-cells'
49
50allOf:
51  - $ref: qcom,gcc.yaml#
52  - if:
53      properties:
54        compatible:
55          contains:
56            enum:
57              - qcom,sm8450-videocc
58              - qcom,sm8550-videocc
59    then:
60      required:
61        - required-opps
62
63unevaluatedProperties: false
64
65examples:
66  - |
67    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
68    #include <dt-bindings/clock/qcom,rpmh.h>
69    #include <dt-bindings/power/qcom,rpmhpd.h>
70    videocc: clock-controller@aaf0000 {
71      compatible = "qcom,sm8450-videocc";
72      reg = <0x0aaf0000 0x10000>;
73      clocks = <&rpmhcc RPMH_CXO_CLK>,
74               <&gcc GCC_VIDEO_AHB_CLK>;
75      power-domains = <&rpmhpd RPMHPD_MMCX>;
76      required-opps = <&rpmhpd_opp_low_svs>;
77      #clock-cells = <1>;
78      #reset-cells = <1>;
79      #power-domain-cells = <1>;
80    };
81...
82