xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml (revision 05d32474ab547fb097cfe3f3eb00a2aa7cdf4067) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Video Clock & Reset Controller on SM8450
8
9maintainers:
10  - Taniya Das <taniya.das@oss.qualcomm.com>
11  - Jagadeesh Kona <quic_jkona@quicinc.com>
12
13description: |
14  Qualcomm video clock control module provides the clocks, resets and power
15  domains on SM8450.
16
17  See also:
18    include/dt-bindings/clock/qcom,glymur-videocc.h
19    include/dt-bindings/clock/qcom,kaanapali-videocc.h
20    include/dt-bindings/clock/qcom,sm8450-videocc.h
21    include/dt-bindings/clock/qcom,sm8650-videocc.h
22    include/dt-bindings/clock/qcom,sm8750-videocc.h
23    include/dt-bindings/clock/qcom,x1p42100-videocc.h
24
25properties:
26  compatible:
27    enum:
28      - qcom,glymur-videocc
29      - qcom,kaanapali-videocc
30      - qcom,sm8450-videocc
31      - qcom,sm8475-videocc
32      - qcom,sm8550-videocc
33      - qcom,sm8650-videocc
34      - qcom,sm8750-videocc
35      - qcom,x1e80100-videocc
36      - qcom,x1p42100-videocc
37
38  clocks:
39    items:
40      - description: Board XO source
41      - description: Video AHB clock from GCC
42
43  power-domains:
44    description:
45      Power domains required for the clock controller to operate
46    items:
47      - description: MMCX power domain
48      - description: MXC power domain
49
50  required-opps:
51    description:
52      OPP nodes that describe required performance points on power domains
53    items:
54      - description: MMCX performance point
55      - description: MXC performance point
56
57required:
58  - compatible
59  - clocks
60  - power-domains
61  - '#power-domain-cells'
62
63allOf:
64  - $ref: qcom,gcc.yaml#
65  - if:
66      properties:
67        compatible:
68          contains:
69            enum:
70              - qcom,glymur-videocc
71              - qcom,kaanapali-videocc
72              - qcom,sm8450-videocc
73              - qcom,sm8550-videocc
74              - qcom,sm8750-videocc
75              - qcom,x1p42100-videocc
76    then:
77      required:
78        - required-opps
79
80unevaluatedProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
85    #include <dt-bindings/clock/qcom,rpmh.h>
86    #include <dt-bindings/power/qcom,rpmhpd.h>
87    videocc: clock-controller@aaf0000 {
88      compatible = "qcom,sm8450-videocc";
89      reg = <0x0aaf0000 0x10000>;
90      clocks = <&rpmhcc RPMH_CXO_CLK>,
91               <&gcc GCC_VIDEO_AHB_CLK>;
92      power-domains = <&rpmhpd RPMHPD_MMCX>,
93                      <&rpmhpd RPMHPD_MXC>;
94      required-opps = <&rpmhpd_opp_low_svs>,
95                      <&rpmhpd_opp_low_svs>;
96      #clock-cells = <1>;
97      #reset-cells = <1>;
98      #power-domain-cells = <1>;
99    };
100...
101