xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml (revision ff124bbbca1d3a07fa1392ffdbbdeece71f68ece) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Graphics Clock & Reset Controller on SM8450
8
9maintainers:
10  - Konrad Dybcio <konradybcio@kernel.org>
11
12description: |
13  Qualcomm graphics clock control module provides the clocks, resets and power
14  domains on Qualcomm SoCs.
15
16  See also::
17    include/dt-bindings/clock/qcom,kaanapali-gpucc.h
18    include/dt-bindings/clock/qcom,milos-gpucc.h
19    include/dt-bindings/clock/qcom,sar2130p-gpucc.h
20    include/dt-bindings/clock/qcom,sm4450-gpucc.h
21    include/dt-bindings/clock/qcom,sm8450-gpucc.h
22    include/dt-bindings/clock/qcom,sm8550-gpucc.h
23    include/dt-bindings/reset/qcom,sm8450-gpucc.h
24    include/dt-bindings/reset/qcom,sm8650-gpucc.h
25    include/dt-bindings/reset/qcom,x1e80100-gpucc.h
26
27properties:
28  compatible:
29    enum:
30      - qcom,kaanapali-gpucc
31      - qcom,milos-gpucc
32      - qcom,sar2130p-gpucc
33      - qcom,sm4450-gpucc
34      - qcom,sm8450-gpucc
35      - qcom,sm8475-gpucc
36      - qcom,sm8550-gpucc
37      - qcom,sm8650-gpucc
38      - qcom,x1e80100-gpucc
39      - qcom,x1p42100-gpucc
40
41  clocks:
42    items:
43      - description: Board XO source
44      - description: GPLL0 main branch source
45      - description: GPLL0 div branch source
46
47required:
48  - compatible
49  - clocks
50  - '#power-domain-cells'
51
52allOf:
53  - $ref: qcom,gcc.yaml#
54
55unevaluatedProperties: false
56
57examples:
58  - |
59    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
60    #include <dt-bindings/clock/qcom,rpmh.h>
61
62    soc {
63        #address-cells = <2>;
64        #size-cells = <2>;
65
66        clock-controller@3d90000 {
67            compatible = "qcom,sm8450-gpucc";
68            reg = <0 0x03d90000 0 0xa000>;
69            clocks = <&rpmhcc RPMH_CXO_CLK>,
70                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
71                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
72            #clock-cells = <1>;
73            #reset-cells = <1>;
74            #power-domain-cells = <1>;
75        };
76    };
77...
78