xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml (revision fbf5df34a4dbcd09d433dd4f0916bf9b2ddb16de) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Graphics Clock & Reset Controller on SM8450
8
9maintainers:
10  - Konrad Dybcio <konradybcio@kernel.org>
11  - Taniya Das <taniya.das@oss.qualcomm.com>
12
13description: |
14  Qualcomm graphics clock control module provides the clocks, resets and power
15  domains on Qualcomm SoCs.
16
17  See also:
18    include/dt-bindings/clock/qcom,glymur-gpucc.h
19    include/dt-bindings/clock/qcom,kaanapali-gpucc.h
20    include/dt-bindings/clock/qcom,milos-gpucc.h
21    include/dt-bindings/clock/qcom,sar2130p-gpucc.h
22    include/dt-bindings/clock/qcom,sm4450-gpucc.h
23    include/dt-bindings/clock/qcom,sm8450-gpucc.h
24    include/dt-bindings/clock/qcom,sm8550-gpucc.h
25    include/dt-bindings/reset/qcom,sm8450-gpucc.h
26    include/dt-bindings/reset/qcom,sm8650-gpucc.h
27    include/dt-bindings/reset/qcom,sm8750-gpucc.h
28    include/dt-bindings/reset/qcom,x1e80100-gpucc.h
29
30properties:
31  compatible:
32    enum:
33      - qcom,glymur-gpucc
34      - qcom,kaanapali-gpucc
35      - qcom,milos-gpucc
36      - qcom,sar2130p-gpucc
37      - qcom,sm4450-gpucc
38      - qcom,sm8450-gpucc
39      - qcom,sm8475-gpucc
40      - qcom,sm8550-gpucc
41      - qcom,sm8650-gpucc
42      - qcom,sm8750-gpucc
43      - qcom,x1e80100-gpucc
44      - qcom,x1p42100-gpucc
45
46  clocks:
47    items:
48      - description: Board XO source
49      - description: GPLL0 main branch source
50      - description: GPLL0 div branch source
51
52  power-domains:
53    items:
54      - description: A phandle to the MX power-domain
55      - description: A phandle to the CX power-domain
56
57  required-opps:
58    items:
59      - description: A phandle to an OPP node describing MX performance points
60      - description: A phandle to an OPP node describing CX performance points
61
62required:
63  - compatible
64  - clocks
65  - '#power-domain-cells'
66
67allOf:
68  - $ref: qcom,gcc.yaml#
69  - if:
70      properties:
71        compatible:
72          contains:
73            enum:
74              - qcom,sm8750-gpucc
75    then:
76      required:
77        - power-domains
78        - required-opps
79
80unevaluatedProperties: false
81
82examples:
83  - |
84    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
85    #include <dt-bindings/clock/qcom,rpmh.h>
86
87    soc {
88        #address-cells = <2>;
89        #size-cells = <2>;
90
91        clock-controller@3d90000 {
92            compatible = "qcom,sm8450-gpucc";
93            reg = <0 0x03d90000 0 0xa000>;
94            clocks = <&rpmhcc RPMH_CXO_CLK>,
95                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
96                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
97            #clock-cells = <1>;
98            #reset-cells = <1>;
99            #power-domain-cells = <1>;
100        };
101    };
102...
103