xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Graphics Clock & Reset Controller on SM8450
8
9maintainers:
10  - Konrad Dybcio <konradybcio@kernel.org>
11
12description: |
13  Qualcomm graphics clock control module provides the clocks, resets and power
14  domains on Qualcomm SoCs.
15
16  See also::
17    include/dt-bindings/clock/qcom,sm4450-gpucc.h
18    include/dt-bindings/clock/qcom,sm8450-gpucc.h
19    include/dt-bindings/clock/qcom,sm8550-gpucc.h
20    include/dt-bindings/reset/qcom,sm8450-gpucc.h
21    include/dt-bindings/reset/qcom,sm8650-gpucc.h
22    include/dt-bindings/reset/qcom,x1e80100-gpucc.h
23
24properties:
25  compatible:
26    enum:
27      - qcom,sm4450-gpucc
28      - qcom,sm8450-gpucc
29      - qcom,sm8550-gpucc
30      - qcom,sm8650-gpucc
31      - qcom,x1e80100-gpucc
32
33  clocks:
34    items:
35      - description: Board XO source
36      - description: GPLL0 main branch source
37      - description: GPLL0 div branch source
38
39required:
40  - compatible
41  - clocks
42  - '#power-domain-cells'
43
44allOf:
45  - $ref: qcom,gcc.yaml#
46
47unevaluatedProperties: false
48
49examples:
50  - |
51    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
52    #include <dt-bindings/clock/qcom,rpmh.h>
53
54    soc {
55        #address-cells = <2>;
56        #size-cells = <2>;
57
58        clock-controller@3d90000 {
59            compatible = "qcom,sm8450-gpucc";
60            reg = <0 0x03d90000 0 0xa000>;
61            clocks = <&rpmhcc RPMH_CXO_CLK>,
62                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
63                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
64            #clock-cells = <1>;
65            #reset-cells = <1>;
66            #power-domain-cells = <1>;
67        };
68    };
69...
70