xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml (revision beaea9c4ba2d8ef1b10223dc3a75a7d7be3e5cd9) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Graphics Clock & Reset Controller on SM8450
8
9maintainers:
10  - Konrad Dybcio <konradybcio@kernel.org>
11
12description: |
13  Qualcomm graphics clock control module provides the clocks, resets and power
14  domains on Qualcomm SoCs.
15
16  See also::
17    include/dt-bindings/clock/qcom,milos-gpucc.h
18    include/dt-bindings/clock/qcom,sar2130p-gpucc.h
19    include/dt-bindings/clock/qcom,sm4450-gpucc.h
20    include/dt-bindings/clock/qcom,sm8450-gpucc.h
21    include/dt-bindings/clock/qcom,sm8550-gpucc.h
22    include/dt-bindings/reset/qcom,sm8450-gpucc.h
23    include/dt-bindings/reset/qcom,sm8650-gpucc.h
24    include/dt-bindings/reset/qcom,x1e80100-gpucc.h
25
26properties:
27  compatible:
28    enum:
29      - qcom,milos-gpucc
30      - qcom,sar2130p-gpucc
31      - qcom,sm4450-gpucc
32      - qcom,sm8450-gpucc
33      - qcom,sm8475-gpucc
34      - qcom,sm8550-gpucc
35      - qcom,sm8650-gpucc
36      - qcom,x1e80100-gpucc
37      - qcom,x1p42100-gpucc
38
39  clocks:
40    items:
41      - description: Board XO source
42      - description: GPLL0 main branch source
43      - description: GPLL0 div branch source
44
45required:
46  - compatible
47  - clocks
48  - '#power-domain-cells'
49
50allOf:
51  - $ref: qcom,gcc.yaml#
52
53unevaluatedProperties: false
54
55examples:
56  - |
57    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
58    #include <dt-bindings/clock/qcom,rpmh.h>
59
60    soc {
61        #address-cells = <2>;
62        #size-cells = <2>;
63
64        clock-controller@3d90000 {
65            compatible = "qcom,sm8450-gpucc";
66            reg = <0 0x03d90000 0 0xa000>;
67            clocks = <&rpmhcc RPMH_CXO_CLK>,
68                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
69                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
70            #clock-cells = <1>;
71            #reset-cells = <1>;
72            #power-domain-cells = <1>;
73        };
74    };
75...
76