xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml (revision 7f4f3b14e8079ecde096bd734af10e30d40c27b7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-dispcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock & Reset Controller for SM8450
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12description: |
13  Qualcomm display clock control module provides the clocks, resets and power
14  domains on SM8450.
15
16  See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
17
18properties:
19  compatible:
20    enum:
21      - qcom,sm8450-dispcc
22      - qcom,sm8475-dispcc
23
24  clocks:
25    minItems: 3
26    items:
27      - description: Board XO source
28      - description: Board Always On XO source
29      - description: Display's AHB clock
30      - description: sleep clock
31      - description: Byte clock from DSI PHY0
32      - description: Pixel clock from DSI PHY0
33      - description: Byte clock from DSI PHY1
34      - description: Pixel clock from DSI PHY1
35      - description: Link clock from DP PHY0
36      - description: VCO DIV clock from DP PHY0
37      - description: Link clock from DP PHY1
38      - description: VCO DIV clock from DP PHY1
39      - description: Link clock from DP PHY2
40      - description: VCO DIV clock from DP PHY2
41      - description: Link clock from DP PHY3
42      - description: VCO DIV clock from DP PHY3
43
44  power-domains:
45    description:
46      A phandle and PM domain specifier for the MMCX power domain.
47    maxItems: 1
48
49  required-opps:
50    description:
51      A phandle to an OPP node describing required MMCX performance point.
52    maxItems: 1
53
54required:
55  - compatible
56  - clocks
57  - '#power-domain-cells'
58
59allOf:
60  - $ref: qcom,gcc.yaml#
61
62unevaluatedProperties: false
63
64examples:
65  - |
66    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
67    #include <dt-bindings/clock/qcom,rpmh.h>
68    #include <dt-bindings/power/qcom,rpmhpd.h>
69    clock-controller@af00000 {
70      compatible = "qcom,sm8450-dispcc";
71      reg = <0x0af00000 0x10000>;
72      clocks = <&rpmhcc RPMH_CXO_CLK>,
73               <&rpmhcc RPMH_CXO_CLK_A>,
74               <&gcc GCC_DISP_AHB_CLK>,
75               <&sleep_clk>,
76               <&dsi0_phy 0>,
77               <&dsi0_phy 1>,
78               <&dsi1_phy 0>,
79               <&dsi1_phy 1>;
80      #clock-cells = <1>;
81      #reset-cells = <1>;
82      #power-domain-cells = <1>;
83      power-domains = <&rpmhpd RPMHPD_MMCX>;
84      required-opps = <&rpmhpd_opp_low_svs>;
85    };
86...
87