xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml (revision f9bff0e31881d03badf191d3b0005839391f5f2b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Camera Clock & Reset Controller on SM8450
8
9maintainers:
10  - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
11
12description: |
13  Qualcomm camera clock control module provides the clocks, resets and power
14  domains on SM8450.
15
16  See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h
17
18properties:
19  compatible:
20    const: qcom,sm8450-camcc
21
22  clocks:
23    items:
24      - description: Camera AHB clock from GCC
25      - description: Board XO source
26      - description: Board active XO source
27      - description: Sleep clock source
28
29  power-domains:
30    maxItems: 1
31    description:
32      A phandle and PM domain specifier for the MMCX power domain.
33
34  required-opps:
35    maxItems: 1
36    description:
37      A phandle to an OPP node describing required MMCX performance point.
38
39  '#clock-cells':
40    const: 1
41
42  '#reset-cells':
43    const: 1
44
45  '#power-domain-cells':
46    const: 1
47
48  reg:
49    maxItems: 1
50
51required:
52  - compatible
53  - reg
54  - clocks
55  - power-domains
56  - required-opps
57  - '#clock-cells'
58  - '#reset-cells'
59  - '#power-domain-cells'
60
61additionalProperties: false
62
63examples:
64  - |
65    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
66    #include <dt-bindings/clock/qcom,rpmh.h>
67    #include <dt-bindings/power/qcom-rpmpd.h>
68    clock-controller@ade0000 {
69      compatible = "qcom,sm8450-camcc";
70      reg = <0xade0000 0x20000>;
71      clocks = <&gcc GCC_CAMERA_AHB_CLK>,
72               <&rpmhcc RPMH_CXO_CLK>,
73               <&rpmhcc RPMH_CXO_CLK_A>,
74               <&sleep_clk>;
75      power-domains = <&rpmhpd SM8450_MMCX>;
76      required-opps = <&rpmhpd_opp_low_svs>;
77      #clock-cells = <1>;
78      #reset-cells = <1>;
79      #power-domain-cells = <1>;
80    };
81...
82