1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Camera Clock & Reset Controller on SM8450 8 9maintainers: 10 - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> 11 - Jagadeesh Kona <quic_jkona@quicinc.com> 12 13description: | 14 Qualcomm camera clock control module provides the clocks, resets and power 15 domains on SM8450. 16 17 See also: 18 include/dt-bindings/clock/qcom,sc8280xp-camcc.h 19 include/dt-bindings/clock/qcom,sm8450-camcc.h 20 include/dt-bindings/clock/qcom,sm8550-camcc.h 21 include/dt-bindings/clock/qcom,sm8650-camcc.h 22 include/dt-bindings/clock/qcom,x1e80100-camcc.h 23 24properties: 25 compatible: 26 enum: 27 - qcom,sc8280xp-camcc 28 - qcom,sm8450-camcc 29 - qcom,sm8475-camcc 30 - qcom,sm8550-camcc 31 - qcom,sm8650-camcc 32 - qcom,x1e80100-camcc 33 34 clocks: 35 items: 36 - description: Camera AHB clock from GCC 37 - description: Board XO source 38 - description: Board active XO source 39 - description: Sleep clock source 40 41 power-domains: 42 maxItems: 1 43 description: 44 A phandle and PM domain specifier for the MMCX power domain. 45 46 required-opps: 47 maxItems: 1 48 description: 49 A phandle to an OPP node describing required MMCX performance point. 50 51 reg: 52 maxItems: 1 53 54required: 55 - compatible 56 - clocks 57 - power-domains 58 59allOf: 60 - $ref: qcom,gcc.yaml# 61 - if: 62 properties: 63 compatible: 64 contains: 65 enum: 66 - qcom,sc8280xp-camcc 67 - qcom,sm8450-camcc 68 - qcom,sm8550-camcc 69 - qcom,x1e80100-camcc 70 then: 71 required: 72 - required-opps 73 74unevaluatedProperties: false 75 76examples: 77 - | 78 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 79 #include <dt-bindings/clock/qcom,rpmh.h> 80 #include <dt-bindings/power/qcom,rpmhpd.h> 81 clock-controller@ade0000 { 82 compatible = "qcom,sm8450-camcc"; 83 reg = <0xade0000 0x20000>; 84 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 85 <&rpmhcc RPMH_CXO_CLK>, 86 <&rpmhcc RPMH_CXO_CLK_A>, 87 <&sleep_clk>; 88 power-domains = <&rpmhpd RPMHPD_MMCX>; 89 required-opps = <&rpmhpd_opp_low_svs>; 90 #clock-cells = <1>; 91 #reset-cells = <1>; 92 #power-domain-cells = <1>; 93 }; 94... 95