xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml (revision 42d37fc0c819b81f6f6afd108b55d04ba9d32d0f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm7150-dispcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock & Reset Controller for SM7150
8
9maintainers:
10  - Danila Tikhonov <danila@jiaxyga.com>
11  - David Wronek <david@mainlining.org>
12  - Jens Reidel <adrian@travitia.xyz>
13
14description: |
15  Qualcomm display clock control module provides the clocks, resets and power
16  domains on SM7150.
17
18  See also:: include/dt-bindings/clock/qcom,sm7150-dispcc.h
19
20properties:
21  compatible:
22    const: qcom,sm7150-dispcc
23
24  clocks:
25    items:
26      - description: Board XO source
27      - description: Board Always On XO source
28      - description: GPLL0 source from GCC
29      - description: Sleep clock source
30      - description: Byte clock from MDSS DSI PHY0
31      - description: Pixel clock from MDSS DSI PHY0
32      - description: Byte clock from MDSS DSI PHY1
33      - description: Pixel clock from MDSS DSI PHY1
34      - description: Link clock from DP PHY
35      - description: VCO DIV clock from DP PHY
36
37  power-domains:
38    maxItems: 1
39    description:
40      CX power domain.
41
42required:
43  - compatible
44  - clocks
45  - power-domains
46
47allOf:
48  - $ref: qcom,gcc.yaml#
49
50unevaluatedProperties: false
51
52examples:
53  - |
54    #include <dt-bindings/clock/qcom,sm7150-gcc.h>
55    #include <dt-bindings/clock/qcom,rpmh.h>
56    #include <dt-bindings/power/qcom,rpmhpd.h>
57    clock-controller@af00000 {
58      compatible = "qcom,sm7150-dispcc";
59      reg = <0x0af00000 0x200000>;
60      clocks = <&rpmhcc RPMH_CXO_CLK>,
61               <&rpmhcc RPMH_CXO_CLK_A>,
62               <&gcc GCC_DISP_GPLL0_CLK_SRC>,
63               <&sleep_clk>,
64               <&mdss_dsi0_phy 0>,
65               <&mdss_dsi0_phy 1>,
66               <&mdss_dsi1_phy 0>,
67               <&mdss_dsi1_phy 1>,
68               <&dp_phy 0>,
69               <&dp_phy 1>;
70      power-domains = <&rpmhpd RPMHPD_CX>;
71      #clock-cells = <1>;
72      #reset-cells = <1>;
73      #power-domain-cells = <1>;
74    };
75...
76