xref: /linux/Documentation/devicetree/bindings/clock/qcom,sm4450-dispcc.yaml (revision 00a37271c8a68070dc64f81a5d64644beb4cef2f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock & Reset Controller on SM4450
8
9maintainers:
10  - Ajit Pandey <quic_ajipan@quicinc.com>
11  - Taniya Das <quic_tdas@quicinc.com>
12
13description: |
14  Qualcomm display clock control module provides the clocks, resets and power
15  domains on SM4450
16
17  See also: include/dt-bindings/clock/qcom,sm4450-dispcc.h
18
19properties:
20  compatible:
21    const: qcom,sm4450-dispcc
22
23  clocks:
24    items:
25      - description: Board XO source
26      - description: Board active XO source
27      - description: Display AHB clock source from GCC
28      - description: sleep clock source
29      - description: Byte clock from DSI PHY0
30      - description: Pixel clock from DSI PHY0
31
32required:
33  - compatible
34  - clocks
35  - '#power-domain-cells'
36
37allOf:
38  - $ref: qcom,gcc.yaml#
39
40unevaluatedProperties: false
41
42examples:
43  - |
44    #include <dt-bindings/clock/qcom,rpmh.h>
45    #include <dt-bindings/clock/qcom,sm4450-gcc.h>
46    clock-controller@af00000 {
47      compatible = "qcom,sm4450-dispcc";
48      reg = <0x0af00000 0x20000>;
49      clocks = <&rpmhcc RPMH_CXO_CLK>,
50               <&rpmhcc RPMH_CXO_CLK_A>,
51               <&gcc GCC_DISP_AHB_CLK>,
52               <&sleep_clk>,
53               <&dsi0_phy_pll_out_byteclk>,
54               <&dsi0_phy_pll_out_dsiclk>;
55      #clock-cells = <1>;
56      #reset-cells = <1>;
57      #power-domain-cells = <1>;
58    };
59...
60